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MC74VHC139M PDF预览

MC74VHC139M

更新时间: 2024-11-03 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 解码器驱动器解复用器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 157K
描述
Dual 2-to-4 Decoder/Demultiplexer

MC74VHC139M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:EIAJ, SOP-16
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.32Is Samacsys:N
系列:AHC/VHC输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:10.2 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.008 A
功能数量:2端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:2/5.5 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):16.5 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:5.275 mmBase Number Matches:1

MC74VHC139M 数据手册

 浏览型号MC74VHC139M的Datasheet PDF文件第2页浏览型号MC74VHC139M的Datasheet PDF文件第3页浏览型号MC74VHC139M的Datasheet PDF文件第4页浏览型号MC74VHC139M的Datasheet PDF文件第5页浏览型号MC74VHC139M的Datasheet PDF文件第6页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC139 is an advanced high speed CMOS 2–to–4 decoder/  
demultiplexer fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
When the device is enabled (E = low), it can be used for gating or as a data  
input for demultiplexing operations. When the enable input is held high, all  
four outputs are fixed high, independent of other inputs.  
D SUFFIX  
16–LEAD SOIC PACKAGE  
CASE 751B–05  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
DT SUFFIX  
16–LEAD TSSOP PACKAGE  
CASE 948F–01  
High Speed: t  
= 5.0ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µΑ (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIH  
NIL CC  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8 V (Max)  
OLP  
M SUFFIX  
16–LEAD SOIC EIAJ PACKAGE  
CASE 966–01  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 100 FETs or 25 Equivalent Gates  
ORDERING INFORMATION  
MC74VHCXXXD  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC  
TSSOP  
SOIC EIAJ  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
2
3
4
5
6
7
Y0a  
Y1a  
A0a  
A1a  
ADDRESS  
INPUTS  
Ea  
1
2
16  
15  
V
CC  
ACTIVE–LOW  
OUTPUTS  
A0a  
Eb  
Y2a  
Y3a  
3
4
14  
13  
A1a  
Y0a  
Y1a  
Y2a  
A0b  
A1b  
Y0b  
1
5
6
12  
11  
Ea  
Y1b  
Y2b  
Y3b  
7
8
10  
9
14  
13  
12  
11  
10  
9
Y3a  
Y0b  
Y1b  
Y2b  
Y3b  
ADDRESS  
INPUTS  
A0b  
A1b  
GND  
ACTIVE–LOW  
OUTPUTS  
FUNCTION TABLE  
15  
Inputs  
A1 A0  
Outputs  
Y0 Y1 Y2 Y3  
Eb  
E
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
H
H
6/97  
REV 0  
Motorola, Inc. 1997  

MC74VHC139M 替代型号

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