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MC74VHC157 PDF预览

MC74VHC157

更新时间: 2024-09-29 23:05:47
品牌 Logo 应用领域
安森美 - ONSEMI 复用器
页数 文件大小 规格书
6页 153K
描述
Quad 2-Channel Multiplexer

MC74VHC157 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC157 is an advanced high speed CMOS quad 2–channel  
multiplexer fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
It consists of four 2–input digital multiplexers with common select (S) and  
enable (E) inputs. When E is held High, selection of data is inhibited and all  
the outputs go Low.  
The select decoding determines whether the A or B inputs get routed to  
the corresponding Y outputs.  
D SUFFIX  
16–LEAD SOIC PACKAGE  
CASE 751B–05  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
DT SUFFIX  
16–LEAD TSSOP PACKAGE  
CASE 948F–01  
High Speed: t  
= 4.1ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2V to 5.5V Operating Range  
= V  
= 28% V  
NIH  
NIL CC  
Low Noise: V  
= 0.8V (Max)  
M SUFFIX  
16–LEAD SOIC EIAJ PACKAGE  
CASE 966–01  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 82 FETs or 20 Equivalent Gates  
ORDERING INFORMATION  
MC74VHCXXXD  
MC74VHCXXXDT  
MC74VHCXXXM  
SOIC  
TSSOP  
SOIC EIAJ  
EXPANDED LOGIC DIAGRAM  
2
A0  
4
3
5
Y0  
B0  
A1  
B1  
PIN ASSIGNMENT  
V
E
S
1
2
16  
15  
CC  
7
A0  
6
Y1  
Y2  
B0  
Y0  
A3  
B3  
Y3  
A2  
3
4
14  
13  
NIBBLE  
INPUTS  
DATA  
OUTPUTS  
11  
10  
A2  
B2  
A3  
B3  
9
A1  
5
6
12  
11  
B1  
14  
13  
B2  
Y2  
7
8
10  
9
Y1  
12  
Y3  
GND  
15  
1
E
S
FUNCTION TABLE  
Inputs  
Outputs  
E
S
Y0 – Y3  
H
L
L
X
L
H
L
A0A3  
B0B3  
A0 – A3, B0 – B3 = the levels of  
the respective Data–Word Inputs.  
6/97  
Motorola, Inc. 1997  
REV 1  

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