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MC74VHC126DTR2 PDF预览

MC74VHC126DTR2

更新时间: 2024-11-24 21:16:35
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 130K
描述
AHC/VHC SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, TSSOP-14

MC74VHC126DTR2 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.09
控制类型:ENABLE HIGH系列:AHC/VHC
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:5 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):15 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mmBase Number Matches:1

MC74VHC126DTR2 数据手册

 浏览型号MC74VHC126DTR2的Datasheet PDF文件第2页浏览型号MC74VHC126DTR2的Datasheet PDF文件第3页浏览型号MC74VHC126DTR2的Datasheet PDF文件第4页浏览型号MC74VHC126DTR2的Datasheet PDF文件第5页浏览型号MC74VHC126DTR2的Datasheet PDF文件第6页浏览型号MC74VHC126DTR2的Datasheet PDF文件第7页 
MC74VHC126  
Quad Bus Buffer  
with 3State Control Inputs  
The MC74VHC126 is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves  
noninverting high speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining CMOS low power dissipation.  
The MC74VHC126 requires the 3state control input (OE) to be set  
Low to place the output into high impedance.  
http://onsemi.com  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
14LEAD SOIC  
D SUFFIX  
CASE 751A  
14LEAD TSSOP  
DT SUFFIX  
CASE 948G  
High Speed: t = 3.8 ns (Typ) at V = 5.0 V  
PD  
CC  
Low Power Dissipation: I = 4.0 μA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
= V  
= 28% V  
PIN CONNECTIONS  
NIH  
NIL CC  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
Designed for 2.0 V to 5.5 V Operating Range  
Y1  
3
4
A4  
Low Noise: V  
= 0.8 V (Max)  
OLP  
OE2  
11 Y4  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
A2  
Y2  
5
6
10 OE3  
9
8
A3  
Y3  
ESD Performance: HBM > 2000 V; Machine Model > 200 V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
These Devices are PbFree and are RoHS Compliant  
GND  
7
(Top View)  
ORDERING INFORMATION  
Device  
MC74VHC126DR2G  
Package  
Shipping  
2500 Units/Reel  
SOIC  
MC74VHC126DTR2G TSSOP 2500 Units/Reel  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 7 of this data sheet.  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 Rev. 5  
MC74VHC126/D  

MC74VHC126DTR2 替代型号

型号 品牌 替代类型 描述 数据表
MC74VHC126DTR2G ONSEMI

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