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MC74VHC125_14 PDF预览

MC74VHC125_14

更新时间: 2024-11-25 01:12:27
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 93K
描述
Quad Bus Buffer

MC74VHC125_14 数据手册

 浏览型号MC74VHC125_14的Datasheet PDF文件第2页浏览型号MC74VHC125_14的Datasheet PDF文件第3页浏览型号MC74VHC125_14的Datasheet PDF文件第4页浏览型号MC74VHC125_14的Datasheet PDF文件第5页浏览型号MC74VHC125_14的Datasheet PDF文件第6页浏览型号MC74VHC125_14的Datasheet PDF文件第7页 
MC74VHC125  
Quad Bus Buffer  
with 3−State Control Inputs  
The MC74VHC125 is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
http://onsemi.com  
The MC74VHC125 requires the 3−state control input (OE) to be set  
High to place the output into the high impedance state.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7 V, allowing the interface of 5 V  
systems to 3 V systems.  
14−LEAD SOIC  
14−LEAD TSSOP  
DT SUFFIX  
D SUFFIX  
CASE 751A  
CASE 948G  
Features  
High Speed: t = 3.8ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
PIN CONNECTION AND  
MARKING DIAGRAM  
High Noise Immunity: V  
= V  
= 28% V  
NIH  
NIL CC  
(Top View)  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
Designed for 2 V to 5.5 V Operating Range  
Low Noise: V  
= 0.8 V (Max)  
OLP  
Y1  
3
4
A4  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
OE2  
11 Y4  
A2  
Y2  
5
6
7
10 OE3  
ESD Performance: Human Body Model; > 2000 V,  
Machine Model; > 200 V  
9
8
A3  
Y3  
GND  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
These Devices are Pb−Free and are RoHS Compliant  
LOGIC DIAGRAM  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
Active−Low Output Enables  
section on page 6 of this data sheet.  
2
3
A1  
Y1  
1
OE1  
ORDERING INFORMATION  
5
4
6
Device  
Package  
Shipping  
A2  
Y2  
Y3  
MC74VHC125DG  
SOIC−14 55 Units / Rail  
(Pb−Free)  
OE2  
9
8
MC74VHC125DR2G  
SOIC−14 2500 / Tape &  
A3  
(Pb−Free)  
Reel  
10  
OE3  
MC74VHC125DTR2G TSSOP−14 2500 / Tape &  
12  
13  
11  
(Pb−Free) Reel  
A4  
Y4  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
OE4  
FUNCTION TABLE  
VHC125  
Inputs Output  
A
OE  
Y
H
L
L
L
H
L
X
H
Z
© Semiconductor Components Industries, LLC, 2014  
1
Publication Order Number:  
September, 2014 − Rev. 7  
MC74VHC125/D  

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