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MC74VHC125DR2G PDF预览

MC74VHC125DR2G

更新时间: 2024-11-25 01:11:27
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
9页 139K
描述
Quad Bus Buffer with 3−State Control Inputs

MC74VHC125DR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.86
控制类型:ENABLE LOW系列:AHC/VHC
JESD-30 代码:R-PDSO-G14JESD-609代码:e3
长度:8.65 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TR
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):16 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:3.9 mm

MC74VHC125DR2G 数据手册

 浏览型号MC74VHC125DR2G的Datasheet PDF文件第2页浏览型号MC74VHC125DR2G的Datasheet PDF文件第3页浏览型号MC74VHC125DR2G的Datasheet PDF文件第4页浏览型号MC74VHC125DR2G的Datasheet PDF文件第5页浏览型号MC74VHC125DR2G的Datasheet PDF文件第6页浏览型号MC74VHC125DR2G的Datasheet PDF文件第7页 
MC74VHC125  
Quad Bus Buffer  
with 3State Control Inputs  
The MC74VHC125 is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
http://onsemi.com  
The MC74VHC125 requires the 3state control input (OE) to be set  
High to place the output into the high impedance state.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7 V, allowing the interface of 5 V  
systems to 3 V systems.  
14LEAD SOIC  
14LEAD TSSOP  
DT SUFFIX  
D SUFFIX  
CASE 751A  
CASE 948G  
High Speed: t = 3.8ns (Typ) at V = 5 V  
PD  
CC  
Low Power Dissipation: I = 4 mA (Max) at T = 25°C  
CC  
A
High Noise Immunity: V  
= V  
= 28% V  
NIH  
NIL CC  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
14LEAD SOIC EIAJ  
M SUFFIX  
CASE 965  
Designed for 2 V to 5.5 V Operating Range  
Low Noise: V  
= 0.8 V (Max)  
OLP  
PIN CONNECTION AND  
MARKING DIAGRAM  
(Top View)  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance: Human Body Model; > 2000 V,  
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
Machine Model; > 200 V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
These Devices are PbFree and are RoHS Compliant  
Y1  
3
4
A4  
OE2  
11 Y4  
A2  
Y2  
5
6
7
10 OE3  
9
8
A3  
Y3  
GND  
DEVICE MARKING INFORMATION  
See general marking information in the device marking  
section on page 6 of this data sheet.  
ORDERING INFORMATION  
Device  
Package  
Shipping  
MC74VHC125DG  
SOIC  
55 Units/Rail  
2500 Units/Reel  
50 Units/Rail  
MC74VHC125DTR2G TSSOP  
MC74VHC125MG  
SOIC EIAJ  
SOIC  
MC74VHC125DR2G  
2500 Units/Reel  
2000 Units/Reel  
MC74VHC125MELG SOEIAJ  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 Rev. 6  
MC74VHC125/D  

MC74VHC125DR2G 替代型号

型号 品牌 替代类型 描述 数据表
MC74VHC125MG ONSEMI

完全替代

Quad Bus Buffer with 3−State Control Inputs
MC74VHC125DG ONSEMI

完全替代

Quad Bus Buffer, 3-State, SOIC-14 NB, 55-TUBE
MC74VHC125D ONSEMI

完全替代

Quad Bus Buffer

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MC74VHC125MELG ONSEMI

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MC74VHC125MG ONSEMI

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MC74VHC125MR2 ONSEMI

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Quad Bus Buffer