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MC74VHC04ML2 PDF预览

MC74VHC04ML2

更新时间: 2024-11-04 15:46:27
品牌 Logo 应用领域
安森美 - ONSEMI 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
5页 135K
描述
IC,LOGIC GATE,HEX INVERTER,AHC/VHC-CMOS,SOP,14PIN,PLASTIC

MC74VHC04ML2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:SOP, SOP14,.3Reach Compliance Code:not_compliant
风险等级:5.92JESD-30 代码:R-PDSO-G14
JESD-609代码:e0负载电容(CL):50 pF
逻辑集成电路类型:INVERTER最大I(ol):0.008 A
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:2/5.5 V
Prop。Delay @ Nom-Sup:8.5 ns认证状态:Not Qualified
施密特触发器:NO子类别:Gates
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MC74VHC04ML2 数据手册

 浏览型号MC74VHC04ML2的Datasheet PDF文件第2页浏览型号MC74VHC04ML2的Datasheet PDF文件第3页浏览型号MC74VHC04ML2的Datasheet PDF文件第4页浏览型号MC74VHC04ML2的Datasheet PDF文件第5页 
SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC04 is an advanced high speed CMOS inverter fabricated  
with silicon gate CMOS technology. It achieves high speed operation similar  
to equivalent Bipolar Schottky TTL while maintaining CMOS low power  
dissipation.  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
D SUFFIX  
14–LEAD SOIC PACKAGE  
CASE 751A–03  
High Speed: t  
= 3.8ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
CC  
NIH  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIL CC  
DT SUFFIX  
14–LEAD TSSOP PACKAGE  
CASE 948G–01  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 36 FETs or 9 Equivalent Gates  
M SUFFIX  
14–LEAD SOIC EIAJ PACKAGE  
CASE 965–01  
LOGIC DIAGRAM  
1
3
5
2
4
6
ORDERING INFORMATION  
A1  
A2  
Y1  
Y2  
MC74VHCXXD  
MC74VHCXXDT  
MC74VHCXXM  
SOIC  
TSSOP  
SOICEIAJ  
A3  
A4  
A5  
A6  
Y3  
Y4  
Y5  
Y6  
FUNCTION TABLE  
Y = A  
Inputs  
A
Outputs  
Y
9
8
10  
12  
L
H
L
11  
13  
H
Pinout: 14–Lead Packages (Top View)  
V
A6  
13  
Y6  
12  
A5  
11  
Y5  
10  
A4  
9
Y4  
8
CC  
14  
1
2
3
4
5
6
7
A1  
Y1  
A2  
Y2  
A3  
Y3  
GND  
6/97  
REV 1  
Motorola, Inc. 1997  

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