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MC74VHC08DTR2G PDF预览

MC74VHC08DTR2G

更新时间: 2024-11-16 05:22:11
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
6页 93K
描述
Quad 2−Input AND Gate

MC74VHC08DTR2G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP14,.25针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:0.51
系列:AHC/VHCJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:AND GATE
最大I(ol):0.008 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:2/5.5 V最大电源电流(ICC):0.02 mA
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):14 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:4.4 mm
Base Number Matches:1

MC74VHC08DTR2G 数据手册

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MC74VHC08  
Quad 2−Input AND Gate  
The MC74VHC08 is an advanced high speed CMOS 2−input AND  
gate fabricated with silicon gate CMOS technology. It achieves high  
speed operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
http://onsemi.com  
MARKING  
DIAGRAMS  
Features  
High Speed: t = 4.3 ns (Typ) at V = 5.0 V  
PD  
CC  
14  
1
Low Power Dissipation: I = 2.0 mA (Max) at T = 25°C  
CC  
A
SOIC−14  
D SUFFIX  
CASE 751A  
VHC08G  
AWLYWW  
High Noise Immunity: V  
= V  
= 28% V  
NIH  
NIL CC  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
Designed for 2.0 V to 5.5 V Operating Range  
Low Noise: V  
= 0.8 V (Max)  
14  
OLP  
VHC  
08  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
TSSOP  
DT SUFFIX  
CASE 948G  
ALYW  
ESD Performance:  
1
Human Body Model > 2000 V;  
Machine Model > 200 V  
Chip Complexity: 24 FETs or 6 Equivalent Gates  
14  
Pb−Free Packages are Available*  
SOEIAJ−14  
M SUFFIX  
CASE 965  
74VHC08  
ALYWG  
1
A1  
3
Y1  
2
1
B1  
4
A2  
A
= Assembly Location  
WL, L = Wafer Lot  
= Year  
6
Y2  
5
B2  
Y
Y = AB  
9
WW, W = Work Week  
G or = Pb−Free Package  
A3  
8
Y3  
10  
B3  
12  
A4  
(Note: Microdot may be in either location)  
11  
Y4  
13  
FUNCTION TABLE  
B4  
Inputs  
Output  
Figure 1. Logic Diagram  
A
B
Y
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
L
L
L
H
L
L
L
14  
H
H
L
H
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 4 of this data sheet.  
1
2
3
4
5
6
7
A1  
B1  
Y1  
A2  
B2  
Y2 GND  
(Top View)  
Figure 2. Pinout: 14−Lead Packages  
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
November, 2005 − Rev. 6  
MC74VHC08/D  

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