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MC74VHC08DTG PDF预览

MC74VHC08DTG

更新时间: 2024-11-04 13:11:19
品牌 Logo 应用领域
安森美 - ONSEMI
页数 文件大小 规格书
5页 141K
描述
AHC/VHC SERIES, QUAD 2-INPUT AND GATE, PDSO14, LEAD FREE, TSSOP-14

MC74VHC08DTG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.12
系列:AHC/VHCJESD-30 代码:R-PDSO-G14
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE最大I(ol):0.008 A
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:RAIL电源:2/5.5 V
Prop。Delay @ Nom-Sup:9 ns传播延迟(tpd):14 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.2 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL宽度:4.4 mm
Base Number Matches:1

MC74VHC08DTG 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHC08 is an advanced high speed CMOS 2–input AND gate  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
The internal circuit is composed of three stages, including a buffer output  
which provides high noise immunity and stable output. The inputs tolerate  
voltages up to 7V, allowing the interface of 5V systems to 3V systems.  
D SUFFIX  
14–LEAD SOIC PACKAGE  
CASE 751A–03  
High Speed: t  
= 4.3ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 2µA (Max) at T = 25°C  
CC  
NIH  
A
High Noise Immunity: V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
= V  
= 28% V  
NIL CC  
DT SUFFIX  
14–LEAD TSSOP PACKAGE  
CASE 948G–01  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 24 FETs or 6 Equivalent Gates  
M SUFFIX  
14–LEAD SOIC EIAJ PACKAGE  
CASE 965–01  
LOGIC DIAGRAM  
ORDERING INFORMATION  
1
A1  
3
MC74VHCXXD  
MC74VHCXXDT  
MC74VHCXXM  
SOIC  
TSSOP  
SOICEIAJ  
Y1  
Y2  
Y3  
Y4  
2
B1  
4
5
A2  
B2  
6
8
Y = AB  
FUNCTION TABLE  
9
A3  
B3  
Inputs  
Output  
Y
10  
A
B
12  
13  
L
L
L
H
L
L
L
A4  
B4  
11  
H
H
L
H
H
Pinout: 14–Lead Packages (Top View)  
V
B4  
13  
A4  
12  
Y4  
11  
B3  
10  
A3  
9
Y3  
8
CC  
14  
1
2
3
4
5
6
7
A1  
B1  
Y1  
A2  
B2  
Y2  
GND  
6/97  
REV 1  
Motorola, Inc. 1997  

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