with 3–State Control Inputs
The MC74VHC125 is a high speed CMOS quad bus buffer
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
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The MC74VHC125 requires the 3–state control input (OE) to be set
High to place the output into the high impedance state.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7V, allowing the interface of 5V systems
to 3V systems.
14–LEAD SOIC
14–LEAD TSSOP
DT SUFFIX
D SUFFIX
CASE 751A
CASE 948G
• High Speed: t
= 3.8ns (Typ) at V
= 5V
PD
• Low Power Dissipation: I
CC
= 4µA (Max) at T = 25°C
CC
A
• High Noise Immunity: V
= V
= 28% V
NIL CC
NIH
• Power Down Protection Provided on Inputs
• Balanced Propagation Delays
• Designed for 2V to 5.5V Operating Range
14–LEAD SOIC EIAJ
M SUFFIX
CASE 965
• Low Noise: V
= 0.8V (Max)
OLP
PIN CONNECTION AND
MARKING DIAGRAM (Top View)
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300mA
• ESD Performance: HBM > 2000V; Machine Model > 200V
• Chip Complexity: 72 FETs or 18 Equivalent Gates
OE1
A1
1
2
14
13 OE4
12
V
CC
Y1
3
4
A4
LOGIC DIAGRAM
OE2
11 Y4
Active–Low Output Enables
A2
Y2
5
6
7
10 OE3
2
1
3
6
A1
9
8
A3
Y3
Y1
GND
OE1
5
4
For detailed package marking information, see the Marking
Diagram section on page 5 of this data sheet.
A2
Y2
Y3
OE2
9
8
A3
ORDERING INFORMATION
10
OE3
Device
Package
SOIC
Shipping
12
13
11
A4
Y4
MC74VHC125D
MC74VHC125DT
MC74VHC125M
55 Units/Rail
96 Units/Rail
50 Units/Rail
OE4
TSSOP
FUNCTION TABLE
SOIC EIAJ
VHC125
Inputs Output
A
OE
Y
H
L
L
L
H
L
X
H
Z
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
April, 2000 – Rev. 2
MC74VHC125/D