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MC74HC74ADR2 PDF预览

MC74HC74ADR2

更新时间: 2024-11-19 23:01:35
品牌 Logo 应用领域
安森美 - ONSEMI 触发器
页数 文件大小 规格书
8页 191K
描述
Dual D Flip-Flop with Set and Reset

MC74HC74ADR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.2系列:HC/UH
JESD-30 代码:R-PDSO-G14JESD-609代码:e0
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A湿度敏感等级:1
位数:1功能数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):235电源:2/6 V
传播延迟(tpd):150 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:24 MHz

MC74HC74ADR2 数据手册

 浏览型号MC74HC74ADR2的Datasheet PDF文件第2页浏览型号MC74HC74ADR2的Datasheet PDF文件第3页浏览型号MC74HC74ADR2的Datasheet PDF文件第4页浏览型号MC74HC74ADR2的Datasheet PDF文件第5页浏览型号MC74HC74ADR2的Datasheet PDF文件第6页浏览型号MC74HC74ADR2的Datasheet PDF文件第7页 
High–Performance Silicon–Gate CMOS  
The MC74HC74A is identical in pinout to the LS74. The device  
inputs are compatible with standard CMOS outputs; with pullup  
resistors, they are compatible with LSTTL outputs.  
This device consists of two D flip–flops with individual Set, Reset,  
and Clock inputs. Information at a D–input is transferred to the  
corresponding Q output on the next positive going edge of the clock  
input. Both Q and Q outputs are available from each flip–flop. The Set  
and Reset inputs are asynchronous.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
PDIP–14  
N SUFFIX  
CASE 646  
MC74HC74AN  
AWLYYWW  
1
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
14  
SOIC–14  
D SUFFIX  
CASE 751A  
HC74A  
AWLYWW  
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
14  
HC  
74A  
ALYW  
TSSOP–14  
DT SUFFIX  
CASE 948G  
Chip Complexity: 128 FETs or 32 Equivalent Gates  
LOGIC DIAGRAM  
1
1
RESET 1  
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
5
6
2
3
DATA 1  
Q1  
Q1  
CLOCK 1  
PIN ASSIGNMENT  
4
SET 1  
PIN 14 = V  
CC  
PIN 7 = GND  
RESET 1  
DATA 1  
1
2
14  
13 RESET 2  
12  
V
CC  
13  
RESET 2  
3
4
CLOCK 1  
SET 1  
DATA 2  
9
8
12  
11  
DATA 2  
Q2  
Q2  
11 CLOCK 2  
10 SET 2  
CLOCK 2  
Q1  
Q1  
5
6
10  
9
8
Q2  
Q2  
SET 2  
GND  
7
FUNCTION TABLE  
Inputs  
Set Reset Clock Data  
Outputs  
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*  
H
L
L
H
H*  
L
ORDERING INFORMATION  
Device  
Package  
PDIP–14  
Shipping  
MC74HC74AN  
2000 / Box  
55 / Rail  
H
L
H
No Change  
No Change  
No Change  
MC74HC74AD  
SOIC–14  
SOIC–14  
TSSOP–14  
TSSOP–14  
MC74HC74ADR2  
MC74HC74ADT  
MC74HC74ADTR2  
2500 / Reel  
96 / Rail  
*Both outputs will remain high as long as Set and Reset are low, but the output  
states are unpredictable if Set and Reset go high simultaneously.  
2500 / Reel  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 8  
MC74HC74A/D  

MC74HC74ADR2 替代型号

型号 品牌 替代类型 描述 数据表
MC74HC74ADR2G ONSEMI

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