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MC74HC75 PDF预览

MC74HC75

更新时间: 2024-09-26 21:53:59
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
5页 175K
描述
Dual 2-Bit Transparent Latch

MC74HC75 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC74HC75 is identical in pinout to the LS75. The device inputs are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
This device consists of two independent 2–bit transparent latches. Each  
latch stores the input data while Latch Enable is at a logic low. The outputs  
follow the data inputs when Latch Enable is at a logic high.  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751B–05  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2 to 6 V  
16  
1
Low Input Current: 1 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
ORDERING INFORMATION  
MC74HCXXN  
MC74HCXXD  
Plastic  
SOIC  
Chip Complexity: 80 FETs or 20 Equivalent Gates  
PIN ASSIGNMENT  
LOGIC DIAGRAM  
Q0  
D0  
1
2
16  
15  
Q0  
Q1  
a
a
a
a
a
2, 6  
D1  
LE  
3
4
14  
13  
Q1  
LE  
16, 10  
a
DATA  
INPUTS  
Q0  
Q0  
Q1  
Q1  
D0  
D1  
3, 7  
1, 11  
15, 9  
14, 8  
b
a
2–BIT  
TRANSPARENT  
LATCH  
V
5
6
12  
11  
GND  
CC  
D0  
Q0  
Q0  
Q1  
b
b
b
b
b
b
D1  
Q1  
7
8
10  
9
13, 4  
LATCH  
ENABLE  
PIN 5 = V  
CC  
PIN 12 = GND  
FUNCTION TABLE  
Inputs  
Latch  
Outputs  
D
Enable  
Q
Q
L
H
X
H
H
L
L
H
Q0  
H
L
Q0  
X = don’t care  
Q0 = latched data  
10/95  
REV 6  
Motorola, Inc. 1995  

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