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MC74HC751D-04ADW

更新时间： 2024-11-20 03:02:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 锁存器
页数 文件大小 规格书
7页 235K
描述
Octal 3-State Noninverting Transparent Latch

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中文翻译

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MC74HC751D-04ADW 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
J SUFFIX  
CERAMIC PACKAGE  
CASE 732–03  
20  
The MC54/74HC573A is identical in pinout to the LS573. The devices are  
compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
These latches appear transparent to data (i.e., the outputs change  
asynchronously) when Latch Enable is high. When Latch Enable goes low,  
data meeting the setup and hold time becomes latched.  
The HC573A is identical in function to the HCT373A but has the data  
inputs on the opposite side of the package from the outputs to facilitate PC  
board layout.  
1
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 738–03  
20  
DW SUFFIX  
SOIC PACKAGE  
CASE 751D–04  
20  
1
1
The HC573A is the noninverting version of the HC563A.  
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
Low Input Current: 1.0 µA  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
DT SUFFIX  
TSSOP PACKAGE  
CASE 948E–02  
20  
ORDERING INFORMATION  
MC54HCXXXAJ  
MC74HCXXXAN  
Ceramic  
Plastic  
•
Chip Complexity: 218 FETs or 54.5 Equivalent Gates  
MC74HCXXXADW SOIC  
MC74HCXXXADT TSSOP  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
2
3
4
19  
18  
17  
D0  
D1  
D2  
Q0  
Q1  
Q2  
OUTPUT  
ENABLE  
1
20  
V
CC  
D0  
2
3
19  
18  
Q0  
Q1  
5
6
16  
15  
NONINVERTING  
OUTPUTS  
DATA  
INPUTS  
D3  
D4  
Q3  
Q4  
D1  
D2  
4
17  
Q2  
7
8
14  
13  
D5  
D6  
D7  
Q5  
Q6  
Q7  
D3  
D4  
5
16  
15  
14  
13  
12  
11  
Q3  
Q4  
Q5  
Q6  
Q7  
6
9
12  
D5  
7
11  
1
LATCH ENABLE  
D6  
8
PIN 20 = V  
CC  
PIN 10 = GND  
D7  
9
OUTPUT ENABLE  
LATCH  
ENABLE  
GND  
10  
Design Criteria  
Value  
Units  
ea.  
ns  
Internal Gate Count*  
54.5  
1.5  
FUNCTION TABLE  
Inputs  
Output  
Internal Gate Propagation Delay  
Internal Gate Power Dissipation  
Output Latch  
Enable Enable  
D
Q
5.0  
µW  
pJ  
L
L
L
H
H
L
H
L
X
X
H
Speed Power Product  
0.0075  
L
No Change  
Z
* Equivalent to a two–input NAND gate.  
H
X
X = Don’t Care  
Z = High Impedance  
10/96  
REV 7  
Motorola, Inc. 1996  
1234567

中文翻译

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