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MC74HC76D PDF预览

MC74HC76D

更新时间: 2024-11-19 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
5页 152K
描述
Dual JK Flip-Flop With Set and Reset

MC74HC76D 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP,
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.89
Is Samacsys:N其他特性:MASTER SLAVE OPERATION
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:J-K FLIP-FLOP
位数:2功能数量:2
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):38 ns
认证状态:Not Qualified座面最大高度:1.75 mm
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:NEGATIVE EDGE
宽度:3.9 mm最小 fmax:20 MHz
Base Number Matches:1

MC74HC76D 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
High–Performance Silicon–Gate CMOS  
The MC74HC76 is identical in pinout to the LS76. The device inputs  
are compatible with Standard CMOS outputs; with pullup resistors, they  
are compatible with LSTTL outputs.  
N SUFFIX  
PLASTIC PACKAGE  
CASE 648–08  
16  
1
Each flip–flop is negative–edge clocked and has active–low asynchro-  
nous Set and Reset inputs.  
D SUFFIX  
16  
SOIC PACKAGE  
CASE 751B–05  
The HC76 is identical in function to the HC112, but has a different  
pinout.  
1
Similar in Function to the LS76 Except When Set and Reset Are  
Low Simultaneously  
ORDERING INFORMATION  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS and TTL  
Operating Voltage Range: 2 to 6V  
MC74HCXXN  
MC74HCXXD  
Plastic  
SOIC  
Low Input Current: 1µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance With the JEDEC Standard No. 7A Requirements  
Chip Complexity: 100 FETs or 25 Equivalent Gates  
Pinout: 16–Lead Packages (Top View)  
Clock1  
Set1  
K1  
1
2
3
4
5
16  
15  
14  
13  
12  
LOGIC DIAGRAM  
2
Q1  
Q1  
GND  
K2  
Set1  
Reset1  
J1  
16  
1
15  
14  
K1  
Clock1  
J1  
Q1  
Q1  
V
CC  
4
Clock2  
Set2  
Q2  
Q2  
J2  
6
7
8
11  
10  
9
3
7
Reset1  
Set2  
Reset2  
12  
6
11  
10  
K2  
Clock2  
J2  
Q2  
Q2  
9
8
PIN 5 = V  
PIN 13 = GND  
Reset2  
CC  
FUNCTION TABLE  
Inputs  
Clock  
Outputs  
Set  
Reset  
J
K
Q
Q
L
H
L
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
H
X
X
X
X
X
X
L
X
X
X
L
H
L
H
X
X
X
H
L
L*  
L
H
L*  
No Change  
L
H
L
H
L
H
H
X
X
X
Toggle  
L
H
No Change  
No Change  
No Change  
* Both outputs will remain low as long as Set and Reset are low, but the output states are  
unpredictable if Set and Reset go high simultaneously.  
10/95  
REV 6  
Motorola, Inc. 1995  

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