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MC74HC74AN PDF预览

MC74HC74AN

更新时间: 2024-11-01 23:01:35
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 233K
描述
Dual D Flip-Flop with Set and Reset

MC74HC74AN 技术参数

生命周期:Transferred零件包装代码:DIP
包装说明:DIP, DIP14,.3针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.15系列:HC/UH
JESD-30 代码:R-PDIP-T14JESD-609代码:e0
长度:18.86 mm负载电容(CL):50 pF
逻辑集成电路类型:D FLIP-FLOP最大频率@ Nom-Sup:20000000 Hz
最大I(ol):0.004 A位数:1
功能数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
电源:2/6 V传播延迟(tpd):30 ns
认证状态:Not Qualified座面最大高度:4.69 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:20 MHz
Base Number Matches:1

MC74HC74AN 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
J SUFFIX  
CERAMIC PACKAGE  
CASE 632–08  
High–Performance Silicon–Gate CMOS  
14  
14  
The MC54/74HC74A is identical in pinout to the LS74. The device inputs  
are compatible with standard CMOS outputs; with pullup resistors, they are  
compatible with LSTTL outputs.  
This device consists of two D flip–flops with individual Set, Reset, and  
Clock inputs. Information at a D–input is transferred to the corresponding Q  
output on the next positive going edge of the clock input. Both Q and Q  
outputs are available from each flip–flop. The Set and Reset inputs are  
asynchronous.  
1
N SUFFIX  
PLASTIC PACKAGE  
CASE 646–06  
1
D SUFFIX  
SOIC PACKAGE  
CASE 751A–03  
14  
Output Drive Capability: 10 LSTTL Loads  
Outputs Directly Interface to CMOS, NMOS, and TTL  
Operating Voltage Range: 2.0 to 6.0 V  
1
DT SUFFIX  
TSSOP PACKAGE  
CASE 948G–01  
14  
Low Input Current: 1.0 µA  
High Noise Immunity Characteristic of CMOS Devices  
In Compliance with the Requirements Defined by JEDEC Standard  
No. 7A  
1
ORDERING INFORMATION  
MC54HCXXAJ  
MC74HCXXAN  
MC74HCXXAD  
MC74HCXXADT  
Ceramic  
Plastic  
SOIC  
Chip Complexity: 128 FETs or 32 Equivalent Gates  
TSSOP  
LOGIC DIAGRAM  
PIN ASSIGNMENT  
1
RESET 1  
RESET 1  
DATA 1  
1
2
14  
13  
V
CC  
5
6
2
3
DATA 1  
Q1  
Q1  
RESET 2  
3
4
12  
11  
CLOCK 1  
SET 1  
DATA 2  
CLOCK 2  
CLOCK 1  
Q1  
Q1  
5
6
10  
9
SET 2  
Q2  
4
SET 1  
13  
RESET 2  
GND  
7
8
Q2  
9
8
12  
DATA 2  
Q2  
Q2  
FUNCTION TABLE  
11  
10  
CLOCK 2  
SET 2  
Inputs  
Set Reset Clock Data  
Outputs  
Q
Q
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
H
L
H*  
H
L
L
H
H*  
L
PIN 14 = V  
CC  
PIN 7 = GND  
H
L
H
No Change  
No Change  
No Change  
* Both outputs will remain high as long as  
Set and Reset are low, but the output  
states are unpredictable if Set and Reset  
go high simultaneously.  
10/95  
REV 6  
Motorola, Inc. 1995  

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