MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P−channel
and N−channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
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Features
MARKING
DIAGRAMS
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
14
PDIP−14
P SUFFIX
CASE 646
MC14069UBCP
AWLYYWWG
• Triple Diode Protection on All Inputs
1
• Pin−for−Pin Replacement for CD4069UB
• Meets JEDEC UB Specifications
14
1
SOIC−14
D SUFFIX
CASE 751A
• These Devices are Pb−Free and are RoHS Compliant
14069UG
AWLYWW
MAXIMUM RATINGS (Voltages Referenced to V
)
SS
Symbol
Parameter
Value
−0.5 to +18.0
Unit
V
14
14
069U
ALYWG
G
V
DD
DC Supply Voltage Range
TSSOP−14
DT SUFFIX
CASE 948G
V , V
in out
Input or Output Voltage Range
(DC or Transient)
−0.5 to V + 0.5
V
DD
I , I
in out
Input or Output Current
(DC or Transient) per Pin
10
mA
1
P
Power Dissipation, per Package
(Note 1)
500
mW
D
14
1
SOEIAJ−14
F SUFFIX
CASE 965
MC14069UB
ALYWG
T
A
Ambient Temperature Range
Storage Temperature Range
−55 to +125
−65 to +150
260
°C
°C
°C
T
stg
T
Lead Temperature
(8−Second Soldering)
L
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
WW, W = Work Week
G or G
= Pb−Free Package
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
(Note: Microdot may be in either location)
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
high−impedance circuit. For proper operation, V and V should be constrained
in
out
to the range V v (V or V ) v V
.
SS
in
out
DD
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V or V ). Unused outputs must be left open.
SS
DD
G
© Semiconductor Components Industries, LLC, 2011
1
Publication Order Number:
June, 2011 − Rev. 9
MC14069UB/D