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MC14069UBCL PDF预览

MC14069UBCL

更新时间: 2024-11-18 22:26:23
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极逻辑集成电路
页数 文件大小 规格书
4页 171K
描述
Hex Inverter

MC14069UBCL 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP,Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.8
系列:4000/14000/40000JESD-30 代码:R-GDIP-T14
JESD-609代码:e0长度:19.495 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
功能数量:6输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, GLASS-SEALED
封装代码:DIP封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
传播延迟(tpd):125 ns认证状态:Not Qualified
座面最大高度:5.08 mm最大供电电压 (Vsup):18 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

MC14069UBCL 数据手册

 浏览型号MC14069UBCL的Datasheet PDF文件第2页浏览型号MC14069UBCL的Datasheet PDF文件第3页浏览型号MC14069UBCL的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC14069UB hex inverter is constructed with MOS P–channel and  
N–channel enhancement mode devices in a single monolithic structure.  
These inverters find primary use where low power dissipation and/or high  
noise immunity is desired. Each of the six inverters is a single stage to  
minimize propagation delays.  
L SUFFIX  
CERAMIC  
CASE 632  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
P SUFFIX  
PLASTIC  
CASE 646  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
Triple Diode Protection on All Inputs (see Page 5–2)  
Pin–for–Pin Replacement for CD4069UB  
Meets JEDEC UB Specifications  
D SUFFIX  
SOIC  
CASE 751A  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
ORDERING INFORMATION  
V
DD  
– 0.5 to + 18.0  
MC14XXXUBCP  
MC14XXXUBCL  
MC14XXXUBD  
Plastic  
Ceramic  
SOIC  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
T
A
= – 55° to 125°C for all packages.  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
PIN ASSIGNMENT  
T
Lead Temperature (8–Second Soldering)  
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
IN 1  
OUT 1  
IN 2  
1
2
3
4
14  
13  
12  
11  
V
DD  
IN 6  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
OUT 6  
IN 5  
OUT 2  
LOGIC DIAGRAM  
CIRCUIT SCHEMATIC  
(1/6 OF CIRCUIT SHOWN)  
IN 3  
5
6
10  
9
OUT 5  
IN 4  
OUT 3  
1
3
5
9
2
V
DD  
V
7
8
OUT 4  
V
V
= PIN 14  
= PIN 7  
SS  
DD  
SS  
4
6
8
INPUT*  
OUTPUT  
11  
13  
10  
12  
V
SS  
* Double diode protection on all  
inputs not shown.  
20 ns  
20 ns  
V
DD  
V
DD  
90%  
14  
OUTPUT  
50%  
10%  
INPUT  
PULSE  
GENERATOR  
V
V
SS  
INPUT  
t
t
PLH  
PHL  
C
L
7
V
OH  
90%  
50%  
10%  
SS  
OUTPUT  
V
OL  
t
t
TLH  
THL  
Figure 1. Switching Time Test Circuit and Waveforms  
REV 3  
1/94  
Motorola, Inc. 1995  

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