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MC14069UBF

更新时间： 2024-09-13 22:58:11
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 175K
描述
Hex Inverter

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MC14069UBF 数据手册

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The MC14069UB hex inverter is constructed with MOS P–channel  
and N–channel enhancement mode devices in a single monolithic  
structure. These inverters find primary use where low power  
dissipation and/or high noise immunity is desired. Each of the six  
inverters is a single stage to minimize propagation delays.  
http://onsemi.com  
• Supply Voltage Range = 3.0 Vdc to 18 Vdc  
• Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
• Triple Diode Protection on All Inputs  
• Pin–for–Pin Replacement for CD4069UB  
• Meets JEDEC UB Specifications  
MARKING  
DIAGRAMS  
14  
PDIP–14  
P SUFFIX  
CASE 646  
MC14069UBCP  
AWLYYWW  
1
14  
SOIC–14  
D SUFFIX  
CASE 751A  
14069U  
AWLYWW  
MAXIMUM RATINGS (Voltages Referenced to V ) (Note 2.)  
SS  
Symbol  
Parameter  
Value  
Unit  
V
1
V
DD  
DC Supply Voltage Range  
–0.5 to +18.0  
14  
V , V  
Input or Output Voltage Range  
(DC or Transient)  
–0.5 to V + 0.5  
V
in out  
DD  
TSSOP–14  
DT SUFFIX  
CASE 948G  
14  
069U  
ALYW  
I , I  
in out  
Input or Output Current  
(DC or Transient) per Pin  
±10  
mA  
1
P
Power Dissipation,  
per Package (Note 3.)  
500  
mW  
14  
1
D
SOEIAJ–14  
F SUFFIX  
CASE 965  
MC14069U  
AWLYWW  
T
A
Ambient Temperature Range  
Storage Temperature Range  
–55 to +125  
–65 to +150  
260  
°C  
°C  
°C  
T
stg  
T
Lead Temperature  
L
(8–Second Soldering)  
A
= Assembly Location  
WL or L = Wafer Lot  
YY or Y = Year  
WW or W = Work Week  
2. Maximum Ratings are those values beyond which damage to the device  
may occur.  
3. Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
ORDERING INFORMATION  
This device contains protection circuitry to guard against damage due to high  
static voltages or electric fields. However, precautions must be taken to avoid  
applications of any voltage higher than maximum rated voltages to this  
Device  
Package  
PDIP–14  
SOIC–14  
Shipping  
high–impedancecircuit. For proper operation, V and V should be constrained  
in  
out  
MC14069UBCP  
MC14069UBD  
MC14069UBDR2  
MC14069UBDT  
2000/Box  
2750/Box  
to the range V  
(V or V  
)
V
DD  
.
SS  
in  
out  
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,  
either V or V ). Unused outputs must be left open.  
SS  
DD  
SOIC–14 2500/Tape & Reel  
96/Rail  
TSSOP–14  
MC14069UBDTEL TSSOP–14 2000/Tape & Reel  
MC14069UBDTR2 TSSOP–14 2500/Tape & Reel  
MC14069UBF  
SOEIAJ–14  
See Note 1.  
See Note 1.  
MC14069UBFEL SOEIAJ–14  
1. For ordering information on the EIAJ version of  
the SOIC packages, please contact your local  
ON Semiconductor representative.  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
March, 2000 – Rev. 3  
MC14069UB/D  
12345678

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