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MC14069UBDCBS PDF预览

MC14069UBDCBS

更新时间: 2024-11-04 13:11:15
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摩托罗拉 - MOTOROLA /
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MC14069UBDCBS 数据手册

 浏览型号MC14069UBDCBS的Datasheet PDF文件第2页浏览型号MC14069UBDCBS的Datasheet PDF文件第3页浏览型号MC14069UBDCBS的Datasheet PDF文件第4页 
SEMICONDUCTOR TECHNICAL DATA  
The MC14069UB hex inverter is constructed with MOS P–channel and  
N–channel enhancement mode devices in a single monolithic structure.  
These inverters find primary use where low power dissipation and/or high  
noise immunity is desired. Each of the six inverters is a single stage to  
minimize propagation delays.  
L SUFFIX  
CERAMIC  
CASE 632  
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
P SUFFIX  
PLASTIC  
CASE 646  
Capable of Driving Two Low–Power TTL Loads or One Low–Power  
Schottky TTL Load Over the Rated Temperature Range  
Triple Diode Protection on All Inputs (see Page 5–2)  
Pin–for–Pin Replacement for CD4069UB  
Meets JEDEC UB Specifications  
D SUFFIX  
SOIC  
CASE 751A  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
ORDERING INFORMATION  
V
DD  
– 0.5 to + 18.0  
MC14XXXUBCP  
MC14XXXUBCL  
MC14XXXUBD  
Plastic  
Ceramic  
SOIC  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
I , I  
in out  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
T
A
= – 55° to 125°C for all packages.  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
PIN ASSIGNMENT  
T
Lead Temperature (8–Second Soldering)  
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.  
Temperature Derating:  
IN 1  
OUT 1  
IN 2  
1
2
3
4
14  
13  
12  
11  
V
DD  
IN 6  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
OUT 6  
IN 5  
OUT 2  
LOGIC DIAGRAM  
CIRCUIT SCHEMATIC  
(1/6 OF CIRCUIT SHOWN)  
IN 3  
5
6
10  
9
OUT 5  
IN 4  
OUT 3  
1
3
5
9
2
V
DD  
V
7
8
OUT 4  
V
V
= PIN 14  
= PIN 7  
SS  
DD  
SS  
4
6
8
INPUT*  
OUTPUT  
11  
13  
10  
12  
V
SS  
* Double diode protection on all  
inputs not shown.  
20 ns  
20 ns  
V
DD  
V
DD  
90%  
14  
OUTPUT  
50%  
10%  
INPUT  
PULSE  
GENERATOR  
V
V
SS  
INPUT  
t
t
PLH  
PHL  
C
L
7
V
OH  
90%  
50%  
10%  
SS  
OUTPUT  
V
OL  
t
t
TLH  
THL  
Figure 1. Switching Time Test Circuit and Waveforms  
REV 3  
1/94  
Motorola, Inc. 1995  

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