Datasheet > MC14070B_06

MC14070B_06

更新时间： 2024-09-14 04:59:31

品牌	Logo	应用领域
安森美 - ONSEMI		栅
页数	文件大小	规格书
7页	134K
描述
CMOS SSI Quad Exclusive OR and NOR Gates

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数据手册

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MC14070B_06 数据手册

MC14070B, MC14077B

CMOS SSI

Quad Exclusive “OR” and “NOR” Gates

The MC14070B quad exclusive OR gate and the MC14077B quad

exclusive NOR gate are constructed with MOS P−channel and

N−channel enhancement mode devices in a single monolithic

structure. These complementary MOS logic gates find primary use

where low power dissipation and/or high noise immunity is desired.

http://onsemi.com

MARKING

DIAGRAMS

Features

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

• Double Diode Protection on All Inputs

PDIP−14

P SUFFIX

CASE 646

MC140xxBCP

AWLYYWWG

• MC14070B − Replacement for CD4030B and CD4070B Types

• MC14077B − Replacement for CD4077B Type

• Pb−Free Packages are Available

SOIC−14

D SUFFIX

CASE 751A

140xxBG

AWLYWW

MAXIMUM RATINGS (Voltages Referenced to V

)

Symbol

Parameter

Value

−0.5 to +18.0

Unit

DC Supply Voltage Range

SOEIAJ−14

F SUFFIX

CASE 965

MC140xxB

ALYWG

V , V

in out

Input or Output Voltage Range

(DC or Transient)

−0.5 to V + 0.5

I , I

Input or Output Current

(DC or Transient) per Pin

±10

in out

WL, L

YY, Y

= Specific Device Code

= Assembly Location

= Wafer Lot

Power Dissipation, per Package

(Note 1)

500

= Year

Ambient Temperature Range

Storage Temperature Range

−55 to +125

−65 to +150

260

°C

WW, W = Work Week

= Pb−Free Package

stg

Lead Temperature

(8−Second Soldering)

ORDERING INFORMATION

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, V and V should be constrained

out

to the range V v (V or V ) v V

out

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either V or V ). Unused outputs must be left open.

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

October, 2006 − Rev. 7

MC14070B/D

12 3 4 5 6 7

中文翻译

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与MC14070B_06相关器件

型号	品牌	获取价格	描述	数据表
MC14070B_11	ONSEMI	获取价格	CMOS SSI Quad Exclusive âORâ and âNORâ
MC14070BAL	MOTOROLA	获取价格	4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, CDIP14, 632-08
MC14070BALD	MOTOROLA	获取价格	4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, CDIP14, 632-08
MC14070BALDS	MOTOROLA	获取价格	4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, CDIP14, 632-08
MC14070BALS	MOTOROLA	获取价格	XOR Gate, CMOS, CDIP14
MC14070BCL	MOTOROLA	获取价格	CMOS SSI Quad Exclusive OR and NOR Gates
MC14070BCP	MOTOROLA	获取价格	CMOS SSI Quad Exclusive OR and NOR Gates
MC14070BCP	ONSEMI	获取价格	CMOS SSI
MC14070BCPD	MOTOROLA	获取价格	4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, PDIP14, PLASTIC, DIP-14
MC14070BCPDS	MOTOROLA	获取价格	4000/14000/40000 SERIES, QUAD 2-INPUT XOR GATE, PDIP14, 646-06

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