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MC14071BCP

更新时间： 2024-01-07 14:06:50
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 330K
描述
B-Suffix Series CMOS Gates

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中文翻译

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MC14071BCP 技术参数

生命周期：Contact Manufacturer包装说明：,
Reach Compliance Code：unknown风险等级：5.48
逻辑集成电路类型：OR GATE

MC14071BCP 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The B Series logic gates are constructed with P and N channel  
enhancement mode devices in a single monolithic structure (Complemen-  
tary MOS). Their primary use is where low power dissipation and/or high  
noise immunity is desired.  
•
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc  
All Outputs Buffered  
Capable of Driving Two Low–power TTL Loads or One Low–power  
Schottky TTL Load Over the Rated Temperature Range.  
Double Diode Protection on All Inputs Except: Triple Diode Protection  
on MC14011B and MC14081B  
Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix  
Devices (Exceptions: MC14068B and MC14078B)  
•
•
L SUFFIX  
CERAMIC  
CASE 632  
P SUFFIX  
PLASTIC  
CASE 646  
D SUFFIX  
SOIC  
CASE 751A  
ORDERING INFORMATION  
MC14XXXBCP  
MC14XXXBCL  
MC14XXXBD  
Plastic  
Ceramic  
SOIC  
T
A
= – 55° to 125°C for all packages.  
MAXIMUM RATINGS* (Voltages Referenced to V  
)
SS  
Symbol  
Parameter  
DC Supply Voltage  
Value  
Unit  
V
V
DD  
– 0.5 to + 18.0  
V , V  
Input or Output Voltage (DC or Transient)  
– 0.5 to V  
DD  
+ 0.5  
V
in out  
l , l  
Input or Output Current (DC or Transient),  
per Pin  
± 10  
mA  
in out  
P
Power Dissipation, per Package†  
Storage Temperature  
500  
mW  
C
D
T
stg  
– 65 to + 150  
260  
T
Lead Temperature (8–Second Soldering)  
C
L
* Maximum Ratings are those values beyond which damage to the device may occur.  
†Temperature Derating:  
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C  
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C  
This device contains protection circuitry to guard against damage  
due to high static voltages or electric fields. However, precautions must  
be taken to avoid applications of any voltage higher than maximum rated  
voltages to this high-impedance circuit. For proper operation, V and  
in  
V
out  
should be constrained to the range V  
SS  
≤ (V or V ) ≤ V .  
in out DD  
Unused inputs must always be tied to an appropriate logic voltage  
level (e.g., either V or V ). Unused outputs must be left open.  
SS DD  
REV 3  
1/94  
Motorola, Inc. 1995  
1234567...11

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MC14071BCP 替代型号

型号 品牌 替代类型 描述 数据表
CD4075BE TI

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