MC14069UBCLDS

更新时间： 2024-09-09 12:58:59

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
4页	171K
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数据手册

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MC14069UBCLDS 数据手册

SEMICONDUCTOR TECHNICAL DATA

The MC14069UB hex inverter is constructed with MOS P–channel and

N–channel enhancement mode devices in a single monolithic structure.

These inverters find primary use where low power dissipation and/or high

noise immunity is desired. Each of the six inverters is a single stage to

minimize propagation delays.

L SUFFIX

CERAMIC

CASE 632

•

Supply Voltage Range = 3.0 Vdc to 18 Vdc

P SUFFIX

PLASTIC

CASE 646

Capable of Driving Two Low–Power TTL Loads or One Low–Power

Schottky TTL Load Over the Rated Temperature Range

Triple Diode Protection on All Inputs (see Page 5–2)

Pin–for–Pin Replacement for CD4069UB

•

Meets JEDEC UB Specifications

D SUFFIX

SOIC

CASE 751A

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol

Parameter

DC Supply Voltage

Value

Unit

ORDERING INFORMATION

– 0.5 to + 18.0

MC14XXXUBCP

MC14XXXUBCL

MC14XXXUBD

Plastic

Ceramic

SOIC

V , V

Input or Output Voltage (DC or Transient)

– 0.5 to V

+ 0.5

in out

I , I

in out

Input or Output Current (DC or Transient),

per Pin

± 10

= – 55° to 125°C for all packages.

Power Dissipation, per Package†

Storage Temperature

500

stg

– 65 to + 150

260

PIN ASSIGNMENT

Lead Temperature (8–Second Soldering)

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

IN 1

OUT 1

IN 2

IN 6

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

OUT 6

IN 5

OUT 2

LOGIC DIAGRAM

CIRCUIT SCHEMATIC

(1/6 OF CIRCUIT SHOWN)

IN 3

OUT 5

IN 4

OUT 3

OUT 4

= PIN 14

= PIN 7

INPUT*

OUTPUT

* Double diode protection on all

inputs not shown.

20 ns

90%

OUTPUT

50%

10%

INPUT

PULSE

GENERATOR

INPUT

PLH

PHL

90%

50%

10%

OUTPUT

TLH

THL

Figure 1. Switching Time Test Circuit and Waveforms

REV 3

1/94

MOTOROLA CMOS LOGIC DATA

Motorola, Inc. 1995

MC14069UB

12 3 4

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