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MC100EPT22MNR4 PDF预览

MC100EPT22MNR4

更新时间: 2024-02-17 04:38:15
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 136K
描述
3.3V Dual LVTTL/LVCMOS to Differential LVPECL to Differential LVPECL

MC100EPT22MNR4 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:DFN
包装说明:DFN-8针数:8
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.67
最大延迟:0.7 ns接口集成电路类型:TTL/CMOS TO PECL TRANSLATOR
JESD-30 代码:S-XDSO-N8JESD-609代码:e0
长度:2 mm位数:1
功能数量:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
输出锁存器或寄存器:NONE输出极性:COMPLEMENTARY
封装主体材料:UNSPECIFIED封装代码:HVSON
封装等效代码:SOLCC8,.08,20封装形状:SQUARE
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):240
电源:3.3 V认证状态:Not Qualified
座面最大高度:1 mm子类别:Level Translators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:2 mm

MC100EPT22MNR4 数据手册

 浏览型号MC100EPT22MNR4的Datasheet PDF文件第2页浏览型号MC100EPT22MNR4的Datasheet PDF文件第3页浏览型号MC100EPT22MNR4的Datasheet PDF文件第4页浏览型号MC100EPT22MNR4的Datasheet PDF文件第5页浏览型号MC100EPT22MNR4的Datasheet PDF文件第6页浏览型号MC100EPT22MNR4的Datasheet PDF文件第7页 
MC100EPT22  
3.3VꢀDual LVTTL/LVCMOS  
to Differential LVPECL  
Translator  
Description  
http://onsemi.com  
The MC100EPT22 is a dual LVTTL/LVCMOS to differential  
LVPECL translator. Because LVPECL (Positive ECL) levels are used  
only +3.3 V and ground are required. The small outline 8lead  
package and the single gate of the EPT22 makes it ideal for those  
applications where space, performance, and low power are at a  
premium. Because the mature MOSAIC 5 process is used, low cost  
and high speed can be added to the list of features.  
MARKING  
DIAGRAMS*  
8
SOIC8  
D SUFFIX  
CASE 751  
KPT22  
ALYW  
8
1
1
G
1
Features  
8
420 ps Typical Propagation Delay  
Maximum Frequency > 1.1 GHz Typical  
TSSOP8  
DT SUFFIX  
CASE 948R  
8
KA22  
ALYWG  
Operating Range: V = 3.0 V to 3.6 V with GND = 0 V  
CC  
G
1
PNP LVTTL Inputs for Minimal Loading  
Q Output Will Default HIGH with Inputs Open  
The 100 Series Contains Temperature Compensation.  
PbFree Packages are Available  
DFN8  
MN SUFFIX  
CASE 506AA  
1
4
A
L
= Assembly Location  
= Wafer Lot  
Y
W
M
G
= Year  
= Work Week  
= Date Code  
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 11  
MC100EPT22/D  

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