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MC100EPT24DR2 PDF预览

MC100EPT24DR2

更新时间: 2024-11-19 22:15:55
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
4页 71K
描述
LVTTL/LVCOMS to Differential LVECL Translator

MC100EPT24DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:7.14最大延迟:0.8 ns
接口集成电路类型:LVTTL/LVCMOS TO LVECL TRANSLATORJESD-30 代码:R-PDSO-G8
JESD-609代码:e0长度:4.9 mm
湿度敏感等级:1标称负供电电压:-3.3 V
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-EMITTER
输出锁存器或寄存器:NONE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:-4.5 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Level Translators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

MC100EPT24DR2 数据手册

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The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL  
translator. Because LVECL levels and LVTTL/LVCMOS levels are  
used, a –3.3V, +3.3V and ground are required. The small outline  
8–lead SOIC package and the single gate of the EPT24 makes it ideal  
for those applications where space, performance, and low power are at  
a premium.  
http://onsemi.com  
The EPT24 is available in the 100E standard and is compatible with  
ECL 100K logic levels.  
8
1
350ps Typical Propagation Delay  
Maximum Frequency > 1.0GHz  
Differential ECL Outputs  
SO–8  
D SUFFIX  
CASE 751  
Small Outline SOIC Package  
PNP LVTTL Inputs for Minimal Loading  
Flow Through Pinouts  
Q Output will default HIGH with inputs open  
ESD Protection: 4000 KV HBM, 200 V MM  
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.  
For Additional Information, See Application Note AND8003/D  
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
MARKING DIAGRAM  
8
1
A = Assembly Location  
L = Wafer Lot  
Y = Year  
KPT24  
ALYW  
W = Work Week  
*For additional information, see Application Note  
AND8002/D  
Transistor Count = 181 devices  
PIN DESCRIPTION  
PIN  
Q, Q  
D
FUNCTION  
Differential LVECL Outputs  
LVTTL Input  
V
1
2
8
7
V
CC  
EE  
V
CC  
Positive Supply  
LVTTL  
D
Q
GND  
Ground  
V
EE  
Negative Supply  
LVECL  
NC  
NC  
3
4
6
5
Q
ORDERING INFORMATION  
GND  
Device  
Package  
Shipping  
MC100EPT24D  
SOIC  
98 Units/Rail  
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram  
MC100EPT24DR2  
SOIC  
2500 Tape & Reel  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
December, 1999 – Rev. 1  
MC100EPT24/D  

MC100EPT24DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EPT24DR2G ONSEMI

完全替代

3.3V LVTTL/LVCMOS to Differential LVECL Translator
MC100EPT24DG ONSEMI

完全替代

3.3V LVTTL/LVCMOS to Differential LVECL Translator
MC100EPT24D ONSEMI

类似代替

LVTTL/LVCOMS to Differential LVECL Translator

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