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MC100EPT24DTR2 PDF预览

MC100EPT24DTR2

更新时间: 2024-02-12 08:52:30
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
8页 136K
描述
3.3V LVTTL/LVCMOS to Differential LVECL Translator

MC100EPT24DTR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:PLASTIC, TSSOP-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.84最大延迟:0.8 ns
接口集成电路类型:LVTTL/LVCMOS TO LVECL TRANSLATORJESD-30 代码:S-PDSO-G8
JESD-609代码:e0长度:3 mm
湿度敏感等级:1标称负供电电压:-3.3 V
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:OPEN-EMITTER
输出锁存器或寄存器:NONE输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):240
电源:-4.5 V认证状态:Not Qualified
座面最大高度:1.1 mm子类别:Level Translators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm

MC100EPT24DTR2 数据手册

 浏览型号MC100EPT24DTR2的Datasheet PDF文件第2页浏览型号MC100EPT24DTR2的Datasheet PDF文件第3页浏览型号MC100EPT24DTR2的Datasheet PDF文件第4页浏览型号MC100EPT24DTR2的Datasheet PDF文件第5页浏览型号MC100EPT24DTR2的Datasheet PDF文件第6页浏览型号MC100EPT24DTR2的Datasheet PDF文件第7页 
MC100EPT24  
3.3VꢀLVTTL/LVCMOS to  
Differential LVECL Translator  
Description  
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL  
translator. Because LVECL levels and LVTTL/LVCMOS levels are  
used, a 3.3 V, +3.3 V and ground are required. The small outline  
8lead package and the single gate of the EPT24 makes it ideal for  
those applications where space, performance, and low power are at a  
premium.  
http://onsemi.com  
MARKING DIAGRAMS*  
8
SOIC8  
D SUFFIX  
CASE 751  
KPT24  
ALYW  
G
8
Features  
1
1
350 ps Typical Propagation Delay  
Maximum Input Clock Frequency > 1.0 GHz Typical  
The 100 Series Contains Temperature Compensation  
1
8
1
TSSOP8  
DT SUFFIX  
CASE 948R  
Operating Range: V = 3.0 V to 3.6 V;  
CC  
8
KA24  
V
EE  
= 3.6 V to 3.0 V; GND = 0 V  
ALYWG  
G
PNP LVTTL Input for Minimal Loading  
Q Output will Default HIGH with Input Open  
PbFree Packages are Available  
DFN8  
MN SUFFIX  
CASE 506AA  
1
4
A
L
= Assembly Location  
= Wafer Lot  
Y
W
M
G
= Year  
= Work Week  
= Date Code  
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 8  
MC100EPT24/D  

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