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MC100EPT25_06 PDF预览

MC100EPT25_06

更新时间: 2024-11-24 05:22:23
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
9页 139K
描述
−3.3V / −5V Differential ECL to +3.3V LVTTL Translator

MC100EPT25_06 数据手册

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MC100EPT25  
−3.3V / −5VꢀDifferential ECL  
to +3.3V LVTTL Translator  
Description  
The MC100EPT25 is a Differential ECL to LVTTL translator. This  
device requires +3.3 V, 3.3 V to 5.2 V, and ground. The small  
outline 8lead package and the single gate of the EPT25 make it ideal  
for applications which require the translation of a clock or data signal.  
http://onsemi.com  
MARKING DIAGRAMS*  
The V output allows the EPT25 to also be used in a singleended  
BB  
input mode. In this mode the V output is tied to the D input for a  
inverting buffer or the D input for a noninverting buffer. If used, the  
BB  
8
8
KPT25  
ALYW  
G
1
V
BB  
pin should be bypassed to ground with at least a 0.01 mF  
capacitor.  
SOIC8  
D SUFFIX  
CASE 751  
1
Features  
1.1 ns Typical Propagation Delay  
Maximum Frequency > 275 MHz Typical  
8
1
8
Operating Range: V = 3.0 V to 3.6 V;  
CC  
1
KP25  
V
EE  
= 5.5 V to 3.0 V; GND = 0 V  
ALYWG  
24 mA TTL Outputs  
Q Output Will Default LOW with Inputs Open or at V  
TSSOP8  
DT SUFFIX  
CASE 948R  
G
EE  
V Output  
BB  
Open Input Default State  
Safety Clamp on Inputs  
PbFree Packages are Available  
1
4
DFN8  
MN SUFFIX  
CASE 506AA  
A
L
= Assembly Location  
= Wafer Lot  
Y
W
M
G
= Year  
= Work Week  
= Date Code  
= PbFree Package  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
December, 2006 Rev. 14  
MC100EPT25/D  

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