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MC100EPT25DR2 PDF预览

MC100EPT25DR2

更新时间: 2024-11-19 22:18:03
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器接口集成电路光电二极管
页数 文件大小 规格书
8页 99K
描述
Differential LVECL/ECL to LVTTL Translator

MC100EPT25DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.13其他特性:LVECL TO ECL TRANSALATION ALSO POSSIBLE
最大延迟:1.6 ns接口集成电路类型:ECL TO TTL TRANSLATOR
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm标称负供电电压:-3.3 V
位数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:TOTEM-POLE
输出锁存器或寄存器:NONE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:-4.5 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Level Translators
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn80Pb20)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

MC100EPT25DR2 数据手册

 浏览型号MC100EPT25DR2的Datasheet PDF文件第2页浏览型号MC100EPT25DR2的Datasheet PDF文件第3页浏览型号MC100EPT25DR2的Datasheet PDF文件第4页浏览型号MC100EPT25DR2的Datasheet PDF文件第5页浏览型号MC100EPT25DR2的Datasheet PDF文件第6页浏览型号MC100EPT25DR2的Datasheet PDF文件第7页 
The MC100EPT25 is a Differential LVECL/ECL to LVTTL  
translator. This device requires +3.3V, 3.3V to –5.2V, and ground.  
The small outline 8–lead SOIC package and the single gate of the  
EPT25 make it ideal for applications which require the translation of a  
clock or data signal.  
The VBB output allows the EPT25 to also be used in a single–ended  
input mode. In this mode the VBB output is tied to the D input for a  
non–inverting buffer or the D input for an inverting buffer. If used, the  
VBB pin should be bypassed to ground via a 0.01mF capacitator.  
http://onsemi.com  
MARKING  
DIAGRAMS*  
8
SO–8  
D SUFFIX  
CASE 751  
HPT25  
ALYW  
8
1
1.1ns Typical Propagation Delay  
275MHz Fmax (Clock bit stream, not pseudo–random)  
Differential LVECL/ECL inputs  
Small Outline SOIC Package  
24mA TTL outputs  
1
8
TSSOP–8  
DT SUFFIX  
CASE 948R  
HR25  
ALYW  
8
1
1
Flow Through Pinouts  
A = Assembly Location  
L = Wafer Lot  
Y = Year  
Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D  
Q Output will default LOW with inputs open or at GND  
ESD Protection: >4000V HBM, >200V MM  
W = Work Week  
*For additional information, see Application Note  
AND8002/D  
V Output  
BB  
New Differential Input Common Mode Range  
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.  
For Additional Information, See Application Note AND8003/D  
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
PIN DESCRIPTION  
PIN  
Q
FUNCTION  
LVTTL Output  
Transistor Count = 111 devices  
D, D  
Differential LVECL Input Pair  
Positive Supply  
V
CC  
V
1
2
8
7
V
CC  
EE  
V
BB  
GND  
Output Reference Voltage  
Ground  
LVTTL  
V
EE  
Negative Supply  
D
Q
D
3
4
6
5
NC  
GND  
ORDERING INFORMATION  
LVECL  
Device  
Package  
Shipping  
MC100EPT25D  
MC100EPT25DR2  
MC100EPT25DT  
SO–8  
98 Units / Rail  
VBB  
SO–8  
2500 / Reel  
98 Units / Rail  
2500 / Reel  
TSSOP–8  
MC100EPT25DTR2 TSSOP–8  
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
May, 2000 – Rev. 1  
MC100EPT25/D  

MC100EPT25DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EPT25DTG ONSEMI

完全替代

−3.3V / −5V Differential ECL to +3.3V LVTTL Translator
MC100EPT25DR2G ONSEMI

完全替代

−3.3V / −5V Differential ECL to +3.3V LVTTL Translator
MC100EPT25DG ONSEMI

完全替代

−3.3V / −5V Differential ECL to +3.3V LVTTL Translator

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