Datasheet > MC100EPT622MNR4G

MC100EPT622MNR4G

更新时间： 2024-11-06 01:11:35

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	137K
描述
3.3V LVTTL/LVCMOS to LVPECL Translator

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MC100EPT622MNR4G 数据手册

MC100EPT622

3.3VꢀLVTTL/LVCMOS to

LVPECL Translator

Description

The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL

translator. Because LVPECL (Positive ECL) levels are used only +3.3 V

and ground are required. The device has an OR−ed enable input which

can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs

(ENTTL). If the inputs are left open, they will default to the enable state.

The device design has been optimized for low channel−to−channel skew.

http://onsemi.com

MARKING

DIAGRAMS*

Features

MC100

EPT622

AWLYYWWG

• 450 ps Typical Propagation Delay

• Maximum Frequency > 1.5 GHz Typical

• PECL Mode

LQFP−32

FA SUFFIX

CASE 873A

• Operating Range: V = 3.0 V to 3.8 V with V = 0 V

• PNP LVTTL Inputs for Minimal Loading

• Q Output Will Default HIGH with Inputs Open

• The 100 Series Contains Temperature Compensation

• Pb−Free Packages are Available*

MC100

EPT622

AWLYYWWG

QFN32

MN SUFFIX

CASE 488AM

= Assembly Location

= Wafer Lot

= Year

= Work Week

G or G = Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

Table 1. TRUTH TABLE

ENPECL

ENTTL

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Publication Order Number:

May, 2011 − Rev. 6

MC100EPT622/D

12 3 4 5 6 7 8

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