MC100EPT24MNR4

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
8页	136K
描述
3.3V LVTTL/LVCMOS to Differential LVECL Translator

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MC100EPT24MNR4 数据手册

MC100EPT24

3.3VꢀLVTTL/LVCMOS to

Differential LVECL Translator

Description

The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL

translator. Because LVECL levels and LVTTL/LVCMOS levels are

used, a −3.3 V, +3.3 V and ground are required. The small outline

8−lead package and the single gate of the EPT24 makes it ideal for

those applications where space, performance, and low power are at a

premium.

http://onsemi.com

MARKING DIAGRAMS*

SOIC−8

D SUFFIX

CASE 751

KPT24

ALYW

Features

• 350 ps Typical Propagation Delay

• Maximum Input Clock Frequency > 1.0 GHz Typical

• The 100 Series Contains Temperature Compensation

TSSOP−8

DT SUFFIX

CASE 948R

• Operating Range: V = 3.0 V to 3.6 V;

KA24

= −3.6 V to −3.0 V; GND = 0 V

ALYWG

• PNP LVTTL Input for Minimal Loading

• Q Output will Default HIGH with Input Open

• Pb−Free Packages are Available

DFN8

MN SUFFIX

CASE 506AA

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Date Code

= Pb−Free Package

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

Publication Order Number:

December, 2006 − Rev. 8

MC100EPT24/D

12 3 4 5 6 7 8

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