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MC100EPT24 PDF预览

MC100EPT24

更新时间: 2024-02-05 06:02:43
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
4页 71K
描述
LVTTL/LVCOMS to Differential LVECL Translator

MC100EPT24 数据手册

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The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL  
translator. Because LVECL levels and LVTTL/LVCMOS levels are  
used, a –3.3V, +3.3V and ground are required. The small outline  
8–lead SOIC package and the single gate of the EPT24 makes it ideal  
for those applications where space, performance, and low power are at  
a premium.  
http://onsemi.com  
The EPT24 is available in the 100E standard and is compatible with  
ECL 100K logic levels.  
8
1
350ps Typical Propagation Delay  
Maximum Frequency > 1.0GHz  
Differential ECL Outputs  
SO–8  
D SUFFIX  
CASE 751  
Small Outline SOIC Package  
PNP LVTTL Inputs for Minimal Loading  
Flow Through Pinouts  
Q Output will default HIGH with inputs open  
ESD Protection: 4000 KV HBM, 200 V MM  
Moisture Sensitivity Level 1, Indefinite Time Out of Drypack.  
For Additional Information, See Application Note AND8003/D  
Flammability Rating: UL–94 code V–0 @ 1/8”,  
Oxygen Index 28 to 34  
MARKING DIAGRAM  
8
1
A = Assembly Location  
L = Wafer Lot  
Y = Year  
KPT24  
ALYW  
W = Work Week  
*For additional information, see Application Note  
AND8002/D  
Transistor Count = 181 devices  
PIN DESCRIPTION  
PIN  
Q, Q  
D
FUNCTION  
Differential LVECL Outputs  
LVTTL Input  
V
1
2
8
7
V
CC  
EE  
V
CC  
Positive Supply  
LVTTL  
D
Q
GND  
Ground  
V
EE  
Negative Supply  
LVECL  
NC  
NC  
3
4
6
5
Q
ORDERING INFORMATION  
GND  
Device  
Package  
Shipping  
MC100EPT24D  
SOIC  
98 Units/Rail  
Figure 1. 8–Lead Pinout (Top View) and Logic Diagram  
MC100EPT24DR2  
SOIC  
2500 Tape & Reel  
Semiconductor Components Industries, LLC, 1999  
1
Publication Order Number:  
December, 1999 – Rev. 1  
MC100EPT24/D  

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