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MC100EP016MNG PDF预览

MC100EP016MNG

更新时间： 2024-09-15 12:58:59
品牌 Logo 应用领域
安森美 - ONSEMI 计数器
页数 文件大小 规格书
14页 200K
描述
100EP SERIES, SYN POSITIVE EDGE TRIGGERED 8-BIT UP BINARY COUNTER, PQCC32, 5 X 5 MM, 1 MM HEIGHT, 0.5 MM PITCH, LEAD FREE, QFN-32

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MC100EP016MNG 技术参数

是否Rohs认证： 符合生命周期：Active
零件包装代码：QFN包装说明：5 X 5 MM, 1 MM HEIGHT, 0.5 MM PITCH, LEAD FREE, QFN-32
针数：32Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.44
其他特性：NECL MODE: 0V VCC WITH VEE = -3.0V TO -5.5V计数方向：UP
系列：100EPJESD-30 代码：S-PQCC-N32
长度：5 mm负载/预设输入：YES
逻辑集成电路类型：BINARY COUNTER最大频率@ Nom-Sup：1000000000 Hz
工作模式：SYNCHRONOUS位数：8
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC32,.2SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE包装方法：TRAY
电源：-4.5 V最大电源电流（ICC）：200 mA
传播延迟（tpd）：0.7 ns认证状态：Not Qualified
座面最大高度：1 mm子类别：Counters
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：ECL温度等级：INDUSTRIAL
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD触发器类型：POSITIVE EDGE
宽度：5 mmBase Number Matches：1

MC100EP016MNG 数据手册

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MC10EP016, MC100EP016  
3.3V / 5VꢀECL 8−Bit  
Synchronous Binary  
Up Counter  
The MC10/100EP016 is a high−speed synchronous, presettable,  
cascadeable 8−bit binary counter. Architecture and operation are the  
same as the MC10E016 in the ECLinPS™ family.  
http://onsemi.com  
MARKING  
The counter features internal feedback to TC gated by the TCLD  
(Terminal Count Load) pin. When TCLD is LOW (or left open, in  
which case it is pulled LOW by the internal pulldowns), the TC  
feedback is disabled, and counting proceeds continuously, with TC  
going LOW to indicate an all−one state. When TCLD is HIGH, the TC  
feedback causes the counter to automatically reload upon TC = LOW,  
thus functioning as a programmable counter. The Qn outputs do not  
need to be terminated for the count function to operate properly. To  
minimize noise and power, unused Q outputs should be left  
unterminated.  
DIAGRAM*  
MCxxx  
EP016  
AWLYYWWG  
LQFP−32  
FA SUFFIX  
CASE 873A  
COUT and COUT provide differential outputs from a single,  
non−cascaded counter or divider application. COUT and COUT  
should not be used in cascade configuration. Only TC should be used  
for a counter or divider cascade chain output.  
A differential clock input has also been added to improve  
performance.  
xxx  
A
WL  
YY  
WW  
G
= 10 or 100  
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
The 100 Series contains temperature compensation.  
*For additional marking information, refer to  
Application Note AND8002/D.  
• 500 ps Typical Propagation Delay  
• PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
with V = 0 V  
EE  
• NECL Mode Operating Range: V = 0 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 12 of this data sheet.  
CC  
with V = −3.0 V to −5.5 V  
EE  
• Open Input Default State  
• Safety Clamp on Inputs  
• Internal TC Feedback (Gated)  
• Addition of COUT and COUT  
• 8−Bit  
• Differential Clock Input  
• V Output  
BB  
• Fully Synchronous Counting and TC Generation  
• Asynchronous Master Reset  
• Pb−Free Packages are Available*  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 − Rev. 11  
MC10EP016/D  
1234567...14

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