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MC100EP05DT PDF预览

MC100EP05DT

更新时间: 2024-11-23 21:54:39
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
10页 88K
描述
3.3V / 5VECL 2-Input Differential AND/NAND

MC100EP05DT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:TSSOP, TSSOP8,.19
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.52其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V
系列:100EJESD-30 代码:S-PDSO-G8
JESD-609代码:e0长度:3 mm
逻辑集成电路类型:AND/NAND GATE功能数量:1
输入次数:2端子数量:8
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP8,.19封装形状:SQUARE
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):240电源:-4.5 V
最大电源电流(ICC):38 mAProp。Delay @ Nom-Sup:0.32 ns
传播延迟(tpd):0.27 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:ECL
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn90Pb10)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3 mm

MC100EP05DT 数据手册

 浏览型号MC100EP05DT的Datasheet PDF文件第2页浏览型号MC100EP05DT的Datasheet PDF文件第3页浏览型号MC100EP05DT的Datasheet PDF文件第4页浏览型号MC100EP05DT的Datasheet PDF文件第5页浏览型号MC100EP05DT的Datasheet PDF文件第6页浏览型号MC100EP05DT的Datasheet PDF文件第7页 
MC10EP05, MC100EP05  
3.3V / 5VꢀECL 2−Input  
Differential AND/NAND  
The MC10/100EP05 is a 2−input differential AND/NAND gate.  
The device is functionally equivalent to the EL05 and LVEL05  
devices. With AC performance much faster than the LVEL05 device,  
the EP05 is ideal for applications requiring the fastest  
AC performance available.  
http://onsemi.com  
The 100 Series contains temperature compensation.  
MARKING DIAGRAMS*  
220 ps Typical Propagation Delay  
Maximum Frequency > 3 GHz Typical  
8
1
8
1
8
HEP05  
ALYW  
KEP05  
ALYW  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
1
with V = 0 V  
SOIC−8  
D SUFFIX  
CASE 751  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
Open Input Default State  
Safety Clamp on Inputs  
Q Output Will Default LOW with Inputs Open or at V  
Pb−Free Package is Available  
8
1
8
1
8
HP05  
ALYW  
KP05  
ALYW  
1
EE  
TSSOP−8  
DT SUFFIX  
CASE 948R  
L = Wafer Lot  
Y = Year  
H = MC10  
K = MC100  
W = Work Week  
A = Assembly Location  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
June, 2004 − Rev. 6  
MC10EP05/D  

MC100EP05DT 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP05MNR4G ONSEMI

完全替代

3.3V / 5V ECL 2−Input Differential AND/NAND
MC10EP05DT ONSEMI

类似代替

3.3V / 5VECL 2-Input Differential AND/NAND
SY10EP05VKC MICREL

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5V/3.3V DIFFERENTIAL AND/NAND

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