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MC100EP05

更新时间： 2024-11-26 21:54:39

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
10页	88K
描述
3.3V / 5VECL 2-Input Differential AND/NAND

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MC100EP05 数据手册

MC10EP05, MC100EP05

3.3V / 5VꢀECL 2−Input

Differential AND/NAND

The MC10/100EP05 is a 2−input differential AND/NAND gate.

The device is functionally equivalent to the EL05 and LVEL05

devices. With AC performance much faster than the LVEL05 device,

the EP05 is ideal for applications requiring the fastest

AC performance available.

http://onsemi.com

The 100 Series contains temperature compensation.

MARKING DIAGRAMS*

• 220 ps Typical Propagation Delay

• Maximum Frequency > 3 GHz Typical

HEP05

ALYW

KEP05

ALYW

• PECL Mode Operating Range: V = 3.0 V to 5.5 V

with V = 0 V

SOIC−8

D SUFFIX

CASE 751

• NECL Mode Operating Range: V = 0 V

with V = −3.0 V to −5.5 V

• Open Input Default State

• Safety Clamp on Inputs

• Q Output Will Default LOW with Inputs Open or at V

• Pb−Free Package is Available

HP05

ALYW

KP05

ALYW

TSSOP−8

DT SUFFIX

CASE 948R

L = Wafer Lot

Y = Year

H = MC10

K = MC100

W = Work Week

A = Assembly Location

*For additional marking information, refer to

Application Note AND8002/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

Semiconductor Components Industries, LLC, 2004

Publication Order Number:

June, 2004 − Rev. 6

MC10EP05/D

12 3 4 5 6 7...10

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