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MC100EP05DR2 PDF预览

MC100EP05DR2

更新时间: 2024-11-23 21:54:39
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
10页 88K
描述
3.3V / 5VECL 2-Input Differential AND/NAND

MC100EP05DR2 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOIC-8
针数:8Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.5
其他特性:NECL MODE: VCC = 0V WITH VEE = -3V TO -5.5V系列:100E
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:AND/NAND GATE
功能数量:1输入次数:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):240
电源:-4.5 V最大电源电流(ICC):38 mA
Prop。Delay @ Nom-Sup:0.32 ns传播延迟(tpd):0.27 ns
认证状态:Not Qualified施密特触发器:NO
座面最大高度:1.75 mm子类别:Gates
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn80Pb20)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
Base Number Matches:1

MC100EP05DR2 数据手册

 浏览型号MC100EP05DR2的Datasheet PDF文件第2页浏览型号MC100EP05DR2的Datasheet PDF文件第3页浏览型号MC100EP05DR2的Datasheet PDF文件第4页浏览型号MC100EP05DR2的Datasheet PDF文件第5页浏览型号MC100EP05DR2的Datasheet PDF文件第6页浏览型号MC100EP05DR2的Datasheet PDF文件第7页 
MC10EP05, MC100EP05  
3.3V / 5VꢀECL 2−Input  
Differential AND/NAND  
The MC10/100EP05 is a 2−input differential AND/NAND gate.  
The device is functionally equivalent to the EL05 and LVEL05  
devices. With AC performance much faster than the LVEL05 device,  
the EP05 is ideal for applications requiring the fastest  
AC performance available.  
http://onsemi.com  
The 100 Series contains temperature compensation.  
MARKING DIAGRAMS*  
220 ps Typical Propagation Delay  
Maximum Frequency > 3 GHz Typical  
8
1
8
1
8
HEP05  
ALYW  
KEP05  
ALYW  
PECL Mode Operating Range: V = 3.0 V to 5.5 V  
CC  
1
with V = 0 V  
SOIC−8  
D SUFFIX  
CASE 751  
EE  
NECL Mode Operating Range: V = 0 V  
CC  
with V = −3.0 V to −5.5 V  
EE  
Open Input Default State  
Safety Clamp on Inputs  
Q Output Will Default LOW with Inputs Open or at V  
Pb−Free Package is Available  
8
1
8
1
8
HP05  
ALYW  
KP05  
ALYW  
1
EE  
TSSOP−8  
DT SUFFIX  
CASE 948R  
L = Wafer Lot  
Y = Year  
H = MC10  
K = MC100  
W = Work Week  
A = Assembly Location  
*For additional marking information, refer to  
Application Note AND8002/D.  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
June, 2004 − Rev. 6  
MC10EP05/D  

MC100EP05DR2 替代型号

型号 品牌 替代类型 描述 数据表
MC100EP05DR2G ONSEMI

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3.3V / 5V ECL 2−Input Differential AND/NAND
MC100EP05DG ONSEMI

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3.3V / 5V ECL 2−Input Differential AND/NAND
MC100EP05D ONSEMI

类似代替

3.3V / 5VECL 2-Input Differential AND/NAND

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100E SERIES, 2-INPUT XOR/XNOR GATE, PDSO8, LEAD FREE, SOIC-8