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MC-458CA726PFB-A80 PDF预览

MC-458CA726PFB-A80

更新时间： 2024-11-04 11:11:15
品牌 Logo 应用领域
尔必达 - ELPIDA 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
16页 152K
描述
8M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE

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MC-458CA726PFB-A80 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIMM包装说明：DIMM, DIMM168
针数：168Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.32
风险等级：5.92访问模式：SINGLE BANK PAGE BURST
最长访问时间：6 ns其他特性：AUTO/SELF REFRESH
最大时钟频率 (fCLK)：125 MHzI/O 类型：COMMON
JESD-30 代码：R-XDMA-N168内存密度：603979776 bit
内存集成电路类型：SYNCHRONOUS DRAM MODULE内存宽度：72
湿度敏感等级：1功能数量：1
端口数量：1端子数量：168
字数：8388608 words字数代码：8000000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：8MX72
输出特性：3-STATE封装主体材料：UNSPECIFIED
封装代码：DIMM封装等效代码：DIMM168
封装形状：RECTANGULAR封装形式：MICROELECTRONIC ASSEMBLY
峰值回流温度（摄氏度）：225电源：3.3 V
认证状态：Not Qualified刷新周期：4096
自我刷新：YES最大待机电流：0.005 A
子类别：Other Memory ICs最大压摆率：1.15 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子形式：NO LEAD端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
Base Number Matches：1

MC-458CA726PFB-A80 数据手册

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DATA SHEET  
MOS INTEGRATED CIRCUIT  
MC-458CA726  
8M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE  
UNBUFFERED TYPE  
Description  
The MC-458CA726EFB and MC-458CA726PFB are 8,388,608 words by 72 bits synchronous dynamic RAM module  
on which 5 pieces of 128M SDRAM : µPD45128163 are assembled.  
This module provides high density and large quantities of memory in a small space without utilizing the surface-  
mounting technology on the printed circuit board.  
Decoupling capacitors are mounted on power supply line for noise reduction.  
Features  
• 8,388,608 words by 72 bits organization (ECC Type)  
• Clock frequency and access time from CLK  
Part number  
/CAS latency  
Clock frequency  
(MAX.)  
Access time from CLK  
(MAX.)  
MC-458CA726EFB-A80  
MC-458CA726EFB-A10  
MC-458CA726PFB-A80  
MC-458CA726PFB-A10  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
CL = 3  
CL = 2  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
6 ns  
6 ns  
6 ns  
7 ns  
6 ns  
6 ns  
6 ns  
7 ns  
125 MHz  
100 MHz  
100 MHz  
77 MHz  
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge  
• Pulsed interface  
• Possible to assert random column address in every cycle  
• Quad internal banks controlled by BA0 and BA1 (Bank Select)  
• Programmable burst-length (1, 2, 4, 8 and full page)  
• Programmable wrap sequence (sequential / interleave)  
• Programmable /CAS latency (2, 3)  
• Automatic precharge and controlled precharge  
• CBR (Auto) refresh and self refresh  
• All DQs have 10 Ω ± 10 % of series resistor  
• Single 3.3 V ± 0.3 V power supply  
• LVTTL compatible  
• 4,096 refresh cycles /64 ms  
• Burst termination by Burst Stop command and Precharge command  
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)  
• Unbuffered type  
• Serial PD  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for  
availability and additional information.  
Document No. E0061N10 (1st edition)  
This product became EOL in September, 2002.  
(Previous No. M13050EJ7V0DS00)  
Date Published January 2001 CP (K)  
Printed in Japan  
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.  
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