Datasheet > M74HCT126

M74HCT126

更新时间： 2024-11-01 23:01:27

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
10页	254K
描述
QUAD BUS BUFFERS 3-STATE

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中文翻译

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数据手册

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M74HCT126 数据手册

M54/74HCT125

M54/74HCT126

QUAD BUS BUFFERS (3-STATE)

HIGH SPEED

t_PD= 12 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT 25 °C

OUTPUT DRIVE CAPABILITY

15 LSTTL LOADS

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

B1R

(Plastic Package)

F1R

(Ceramic Package)

SYMMETRICAL OUTPUT IMPEDANCE

I_OL= I_OH= 6 mA (MIN.)

COMPATIBLE WITH TTL OUTPUTS

V_IH= 2V (MIN.) V_IL= 0.8V (MAX)

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS125/126

M1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M54HCTXXXF1R

M74HCTXXXB1R

M74HCTXXXM1R

M74HCTXXXC1R

DESCRIPTION

The M54/74HCT125/126 are high speed CMOS

QUAD BUS BUFFER (3-STATE) FABRICATED IN

SILICON GATE C²MOS technology. They have the

same high speed performance ofLSTTL combined

with true CMOS low power consumption. These de-

vices require the same 3-STATE control input G to

be takenhigh to make the output go into the high im-

pedance state.This integrated circuit has input and

output characteristics that are fully compatible with

54/74 LSTTL logic families. M54/74HCT devices

are designed to directly interface HSC²MOS sys-

tems with TTL and NMOS components. They are

also plug in replacements for LSTTL devices giving

a reduction of power consumption. All inputs are

equipped with protection circuits against static dis-

charge and transient excess voltage.

PIN CONNECTIONS (top view)

HCT125

INPUT AND OUTPUT EQUIVALENT CIRCUIT

HCT126

NC =

No Internal

Connection

October 1993

1/10

12 3 4 5 6 7...10

中文翻译

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