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M74HCT132B1R PDF预览

M74HCT132B1R

更新时间: 2024-11-01 23:01:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
7页 53K
描述
QUAD 2-INPUT SCHMITT NAND GATE

M74HCT132B1R 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DIP
包装说明:PLASTIC, DIP-14针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.26Is Samacsys:N
系列:HCTJESD-30 代码:R-PDIP-T14
JESD-609代码:e4负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:45 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:5.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:7.62 mmBase Number Matches:1

M74HCT132B1R 数据手册

 浏览型号M74HCT132B1R的Datasheet PDF文件第2页浏览型号M74HCT132B1R的Datasheet PDF文件第3页浏览型号M74HCT132B1R的Datasheet PDF文件第4页浏览型号M74HCT132B1R的Datasheet PDF文件第5页浏览型号M74HCT132B1R的Datasheet PDF文件第6页浏览型号M74HCT132B1R的Datasheet PDF文件第7页 
M74HCT132  
QUAD 2-INPUT SCHMITT NAND GATE  
PRELIMINARY DATA  
HIGH SPEED: tPD = 20 ns (TYP.) at VCC = 4.5V  
LOWPOWER DISSIPATION:  
CC = 1 µA (MAX.) at TA =25 oC  
I
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
HIGH NOISE IMMUNITY  
VH (TYP.) = 0.71V AT VCC =4.5V  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL =4 mA (MIN)  
BALANCED PROPAGATION DELAYS:  
tPLH tPHL  
B1R  
(Plastic Package)  
M1R  
(Micro Package)  
ORDER CODES :  
M74HCT132B1R  
M74HCT132M1R  
configuration and function are identical to those  
of the M74HCT00.  
The hysteresis characteristics (around 15% VCC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 132  
)
of all inputs allow slowly charging input signals to  
be transformed into sharply defined jitter-free  
output signals.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
DESCRIPTION  
The M74HCT132 is a high speed CMOS QUAD  
2-INPUT SCHMITT NAND GATE fabricated in  
silicon gate C2MOS tecnology. It has the same  
high speed performance of LSTTL combined with  
true COMS low power consumption. Pin  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
June 1998  

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