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M74HCT137RM13TR PDF预览

M74HCT137RM13TR

更新时间: 2024-11-02 14:53:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动双倍数据速率输入元件光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
11页 75K
描述
HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, SOP-16

M74HCT137RM13TR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP-16针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.52
Is Samacsys:N其他特性:ADDRESS LATCHES; 2 ENABLE INPUTS
系列:HCT输入调节:STANDARD
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.004 A
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:56 ns
传播延迟(tpd):56 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

M74HCT137RM13TR 数据手册

 浏览型号M74HCT137RM13TR的Datasheet PDF文件第2页浏览型号M74HCT137RM13TR的Datasheet PDF文件第3页浏览型号M74HCT137RM13TR的Datasheet PDF文件第4页浏览型号M74HCT137RM13TR的Datasheet PDF文件第5页浏览型号M74HCT137RM13TR的Datasheet PDF文件第6页浏览型号M74HCT137RM13TR的Datasheet PDF文件第7页 
M74HCT137  
3 TO 8 LINE DECODER/LATCH (INVERTING)  
HIGH SPEED:  
=17ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
DIP  
SOP  
TSSOP  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
V
CC  
ORDER CODES  
PACKAGE  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 137  
TUBE  
T & R  
DIP  
SOP  
M74HCT137B1R  
M74HCT137M1R M74HCT137RM13TR  
M74HCT137TTR  
DESCRIPTION  
The M74HCT137 is an high speed CMOS 3 TO 8  
LINE DECODER/LATCH (INVERTING) fabricated  
TSSOP  
2
with silicon gate C MOS technology.  
are high unless G1 is high and G2 is low. The  
74HCT137 is ideally suited for the implementation  
of glitch-free decoders in stored-address  
application in bus oriented systems.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
This device is a 3 to 8 line decoder with latches on  
the three address inputs. When GL goes from low  
to high, the addresses present at the select inputs  
(A, B, and C) is stored in the latches. As long as  
GL remains high no address changes will be  
recognized. Output enable pins G1 and G2,  
control the state of the outputs independently of  
the select or latch-enable inputs. All the outputs  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
September 2001  
1/11  

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