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M74HCT138RM13TR PDF预览

M74HCT138RM13TR

更新时间: 2024-11-17 22:25:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
9页 280K
描述
3 TO 8 LINE DECODER (INVERTING)

M74HCT138RM13TR 数据手册

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M74HCT138  
3 TO 8 LINE DECODER (INVERTING)  
HIGH SPEED:  
= 16ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 138  
TUBE  
T & R  
DIP  
SOP  
M74HCT138B1R  
M74HCT138M1R M74HCT138RM13TR  
M74HCT138TTR  
DESCRIPTION  
The M74HCT138 is an high speed CMOS 3 TO 8  
LINE DECODER fabricated with silicon gate  
TSSOP  
2
C MOS technology.  
enable inputs are provided to ease cascade  
connection and application of address decoders  
for memory systems.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
If the device is enabled, 3 binary select inputs (A,  
B, and C) determine which one of the outputs will  
go low. If enable input G1 is held low or either G2A  
or G2B is held high, the decoding function is  
inhibited and all the 8 outputs go high. Three  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/9  

M74HCT138RM13TR 替代型号

型号 品牌 替代类型 描述 数据表
MC74HCT138ADR2G ONSEMI

类似代替

1−of−8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High−Performa
MC74HCT138ADG ONSEMI

类似代替

1−of−8 Decoder/ Demultiplexer with LSTTL Compatible Inputs High−Performa

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