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M74HCT137B1N PDF预览

M74HCT137B1N

更新时间： 2024-11-02 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器驱动器锁存器逻辑集成电路光电二极管输入元件双倍数据速率
页数 文件大小 规格书
12页 262K
描述
HCT SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDIP16, PLASTIC, DIP-16

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中文翻译

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M74HCT137B1N 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：DIP, DIP16,.3
针数：16Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.56其他特性：ADDRESS LATCHES; 2 ENABLE INPUTS
系列：HCTJESD-30 代码：R-PDIP-T16
JESD-609代码：e0负载电容（CL）：50 pF
逻辑集成电路类型：OTHER DECODER/DRIVER最大I（ol）：0.004 A
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP16,.3
封装形状：RECTANGULAR封装形式：IN-LINE
峰值回流温度（摄氏度）：NOT SPECIFIED电源：5 V
Prop。Delay @ Nom-Sup：65 ns传播延迟（tpd）：56 ns
认证状态：Not Qualified座面最大高度：5.1 mm
子类别：Decoder/Drivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.62 mmBase Number Matches：1

M74HCT137B1N 数据手册

 浏览型号M74HCT137B1N的Datasheet PDF文件第2页浏览型号M74HCT137B1N的Datasheet PDF文件第3页浏览型号M74HCT137B1N的Datasheet PDF文件第4页浏览型号M74HCT137B1N的Datasheet PDF文件第5页浏览型号M74HCT137B1N的Datasheet PDF文件第6页浏览型号M74HCT137B1N的Datasheet PDF文件第7页 
M54HCT137  
M74HCT137  
3 TO 8 LINE DECODER/LATCH (INVERTING)  
.
.
.
.
.
.
.
HIGH SPEED  
PD = 17 ns (TYP.) AT VCC = 5 V  
t
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
COMPATIBLE WITH TTL OUTPUTS  
VIH = 2V (MIN.) VIL = 0.8V (MAX)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS137  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
DESCRIPTION  
ORDER CODES :  
The M54/74HCT137 is a high speed CMOS3TO8LINE  
DECODER/LATCH (INVERTING) fabricated in silicon  
gateC2MOStechnology. Ithas the samehigh speed per-  
formance ofLSTTL combined with trueCMOSlow power  
consumption. This device is a 3 to 8 line decoder with lat-  
ches on the three address inputs. When GL goes from low  
to high, the address present at the select inputs (A, B and  
C) is stored in the latches. As long as GL remains high no  
address changes will be recognized. Output enable pins  
G1 and G2, control the state of the outputs independently  
ofthe select orlatch-enable inputs. All theoutputs are high  
unless G1 is high and G2 is low. The HC137 is ideally  
suited for the implementation of glitch-free decoders in  
stored-address applications in bus oriented systems. All  
inputs are equipped with protection circuits against static  
discharge and transient excess voltage.This integrated  
circuit has input and output characteristics that are fully  
compatible with 54/74 LSTTL logic families. M54/74HCT  
devices aredesigned todirectly interfaceHSC2MOS sys-  
temswithTTL and NMOScomponents. They arealso  
plug in replacements for LSTTL devices giving a re-  
duction of power consumption.  
M54HCT137F1R  
M74HCT137B1R  
M74HCT137M1R  
M74HCT137C1R  
PIN CONNECTIONS (top view)  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
February 1993  
1/12  
1234567...12

中文翻译

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