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M74HCT132RM13TR PDF预览

M74HCT132RM13TR

更新时间: 2024-11-02 05:10:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
8页 180K
描述
QUAD 2-INPUT SCHMITT NAND GATE

M74HCT132RM13TR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP-14针数:14
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.36Is Samacsys:N
系列:HCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:5 VProp。Delay @ Nom-Sup:45 ns
传播延迟(tpd):45 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

M74HCT132RM13TR 数据手册

 浏览型号M74HCT132RM13TR的Datasheet PDF文件第2页浏览型号M74HCT132RM13TR的Datasheet PDF文件第3页浏览型号M74HCT132RM13TR的Datasheet PDF文件第4页浏览型号M74HCT132RM13TR的Datasheet PDF文件第5页浏览型号M74HCT132RM13TR的Datasheet PDF文件第6页浏览型号M74HCT132RM13TR的Datasheet PDF文件第7页 
M74HCT132  
QUAD 2-INPUT SCHMITT NAND GATE  
HIGH SPEED:  
= 19ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 1µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY :  
V = 0.7V (TYP) at V = 4.5V  
H
cc  
DIP  
SOP  
TSSOP  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 132  
TUBE  
T & R  
DIP  
SOP  
M74HCT132B1R  
M74HCT132M1R M74HCT132RM13TR  
M74HCT132TTR  
DESCRIPTION  
The M74HCT132 is an high speed CMOS QUAD  
2-INPUT SCHMITT NAND GATE fabricated with  
silicon gate C MOS technology.  
Pin configuration and function are the same as  
those of the M74HCT00. The hysteresis  
TSSOP  
2
The M74HCT132 is designed to directly interface  
HSC MOS systems with TTL and NMOS  
components.  
2
characteristics (around 20% V ) of all inputs allow  
slowly changing input signals to be transformed  
into sharply defined jitter-free output signals.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
cc  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/8  

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