Datasheet > M74HCT126M1R

M74HCT126M1R

更新时间： 2024-02-04 14:20:01

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
9页	171K
描述
QUAD BUS BUFFER (3-STATE)

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中文翻译

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数据手册

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M74HCT126M1R 数据手册

M74HCT126

QUAD BUS BUFFER (3-STATE)

■

HIGH SPEED:

= 13ns (TYP.) at V = 4.5V

LOW POWER DISSIPATION:

= 4µA(MAX.) at T =25°C

COMPATIBLE WITH TTL OUTPUTS :

= 2V (MIN.) V = 0.8V (MAX)

DIP

SOP

TSSOP

BALANCED PROPAGATION DELAYS:

PLH

PHL

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 6mA (MIN)

ORDER CODES

PACKAGE

TUBE

T & R

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 126

DIP

SOP

M74HCT126B1R

M74HCT126M1R M74HCT126RM13TR

M74HCT126TTR

TSSOP

DESCRIPTION

The M74HCT126 is an high speed CMOS QUAD

BUFFER (3-STATE) fabricated with silicon gate

C MOS technology.

The M74HCT126 is designed to directly interface

HSC MOS systems with TTL and NMOS

components.

The device requires the 3-STATE control input G

to be set low to place the output in to the high

impedance state.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

PIN CONNECTION AND IEC LOGIC SYMBOLS

August 2001

1/9

12 3 4 5 6 7...9

中文翻译

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