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M74HCT125M1R PDF预览

M74HCT125M1R

更新时间: 2024-11-01 22:34:27
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
9页 172K
描述
QUAD BUS BUFFER (3-STATE)

M74HCT125M1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.25
控制类型:ENABLE LOW系列:HCT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):150 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.006 A
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
电源:5 VProp。Delay @ Nom-Sup:32 ns
传播延迟(tpd):41 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:3.9 mmBase Number Matches:1

M74HCT125M1R 数据手册

 浏览型号M74HCT125M1R的Datasheet PDF文件第2页浏览型号M74HCT125M1R的Datasheet PDF文件第3页浏览型号M74HCT125M1R的Datasheet PDF文件第4页浏览型号M74HCT125M1R的Datasheet PDF文件第5页浏览型号M74HCT125M1R的Datasheet PDF文件第6页浏览型号M74HCT125M1R的Datasheet PDF文件第7页 
M74HCT125  
QUAD BUS BUFFER (3-STATE)  
HIGH SPEED:  
= 13ns (TYP.) at V = 4.5V  
t
PD  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
COMPATIBLE WITH TTL OUTPUTS :  
= 2V (MIN.) V = 0.8V (MAX)  
V
IH  
IL  
DIP  
SOP  
TSSOP  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 6mA (MIN)  
ORDER CODES  
PACKAGE  
OH  
OL  
TUBE  
T & R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 125  
DIP  
SOP  
M74HCT125B1R  
M74HCT125M1R M74HCT125RM13TR  
M74HCT125TTR  
TSSOP  
DESCRIPTION  
The M74HCT125 is an high speed CMOS QUAD  
BUFFER (3-STATE) fabricated with silicon gate  
C MOS technology.  
The M74HCT125 is designed to directly interface  
HSC MOS systems with TTL and NMOS  
components.  
2
2
The device requires the 3-STATE control input G  
to be set high to place the output in to the high  
impedance state.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
August 2001  
1/9  

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