Datasheet > M54HC107F1R

M54HC107F1R

更新时间： 2024-11-03 22:06:47

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器
页数	文件大小	规格书
11页	251K
描述
DUAL J-K FLIP FLOP WITH CLEAR

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中文翻译

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数据手册

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M54HC107F1R 数据手册

M54HC107

M74HC107

DUAL J-K FLIP FLOP WITH CLEAR

HIGH SPEED

f_MAX= 75 MHz (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 2 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

IOH = I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE WITH

54/74LS107

ORDER CODES :

M54HC107F1R

M74HC107B1R

M74HC107M1R

M74HC107C1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC107 is a high speed CMOS DUAL J-

K FLIPFLOP fabricated in silicon gate C²MOS tech-

nology. It has the same high speed performance of

LSTTL combined with true CMOS low power con-

sumption. These flip-flop are edge sensitive to the

clock input and change state on the negative going

transition of the clock pulse. Each one has inde-

pendent J, K, CLOCK, and CLEAR input and Q and

Q outputs. CLEAR is independent of the clock and

accomplished by a logic low on the input. All inputs

are equipped with protection circuits against static

discharge and transient excess voltage.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

October 1992

1/11

12 3 4 5 6 7...11

中文翻译

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