M54HC109F1

更新时间： 2024-11-04 12:58:03

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器锁存器逻辑集成电路
页数	文件大小	规格书
11页	251K
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中文翻译

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数据手册

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M54HC109F1 数据手册

M54HC109

M74HC109

DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

HIGH SPEED

_MAX= 63 MHz (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

_CC= 2 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

I_OH= I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS109

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

ORDER CODES :

M54HC109F1R

M74HC109B1R

M74HC109M1R

M74HC109C1R

DESCRIPTION

The M54/74HC109 is a high speed CMOS DUAL J-

K FLIP-FLOP WITH PRESET AND CLEAR fabri-

cated in silicon gate C²MOS technology.

PIN CONNECTIONS (top view)

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

In accordance with the logic level on the J and K

input is device changes state on positive going tran-

sitions of the clock pulse. CLEAR and PRESET are

independent of the clock and accomplished bya low

logic level on the corresponding input.

All inputs are equipped with protection circuits

against static discharge and transient excess volt-

age.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

December 1992

1/11

12 3 4 5 6 7...11

中文翻译

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与M54HC109F1相关器件

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