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M54HC109F1 PDF预览

M54HC109F1

更新时间: 2024-02-15 09:21:05
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路
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M54HC109F1 数据手册

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M54HC109  
M74HC109  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
.
.
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.
.
.
.
HIGH SPEED  
MAX = 63 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
CC = 2 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
NIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS109  
f
I
V
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC109F1R  
M74HC109B1R  
M74HC109M1R  
M74HC109C1R  
DESCRIPTION  
The M54/74HC109 is a high speed CMOS DUAL J-  
K FLIP-FLOP WITH PRESET AND CLEAR fabri-  
cated in silicon gate C2MOS technology.  
PIN CONNECTIONS (top view)  
It has the same high speed performance of LSTTL  
combined with true CMOS low power consumption.  
In accordance with the logic level on the J and K  
input is device changes state on positive going tran-  
sitions of the clock pulse. CLEAR and PRESET are  
independent of the clock and accomplished bya low  
logic level on the corresponding input.  
All inputs are equipped with protection circuits  
against static discharge and transient excess volt-  
age.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
December 1992  
1/11  

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