Datasheet > M54HC11

M54HC11

更新时间： 2024-11-03 22:46:39

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
9页	236K
描述
TRIPLE 3-INPUT AND GATE

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中文翻译

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数据手册

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M54HC11 数据手册

M54HC11

M74HC11

TRIPLE 3-INPUT AND GATE

HIGH SPEED

t_PD= 7 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 1 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

IOH = I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE WITH

54/74LS11

ORDER CODES :

M54HC11F1R

M74HC11B1R

M74HC11M1R

M74HC11C1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC11 is a high speed CMOS TRIPLE

3-INPUT AND GATE fabricated in silicon gate

C²MOS technology.

It has the same high speed performance of LSTTL

combined with true CMOS low power consumption.

The internal circuit is composed of 4 stages includ-

ing bufferedoutput, which gives highnoise immunity

and a stable output. All inputs areequipped with pro-

tectioncircuits against static discharge and transient

excess voltage.

INPUT AND OUTPUT EQUIVALENT CIRCUIT

NC =

No Internal

Connection

February 1993

1/9

12 3 4 5 6 7...9

中文翻译

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