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M54HC112 PDF预览

M54HC112

更新时间: 2024-11-03 22:46:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 253K
描述
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M54HC112 数据手册

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M54HC112  
M74HC112  
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
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HIGH SPEED  
fMAX = 67 MHz (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 2 µA AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS112  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
ORDER CODES :  
M54HC112F1R  
M74HC112B1R  
M74HC112M1R  
M74HC112C1R  
DESCRIPTION  
The M54/74HC112 is a high speed CMOS DUAL J-K  
FLIP-FLOP WITH PRESET AND CLEAR fabricated in  
silicon gate C2MOS technology. It has the same high  
speed performance of LSTTL combined with true  
PIN CONNECTIONS (top view)  
CMOS  
low  
power  
consumption.  
The  
M54HC112/M74HC112 dual JK flip-flop features indi-  
vidual J,K, clock, and asynchronous set and clearinputs  
for each flip-flop. When the clock goes high, the inputs  
are enabled and data will be accepted. The logic level  
of the J and K inputs may be allowed to change when  
the clock pulse is high and the bistable will function as  
shown in the truth table. Input data is transferred to the  
input on the negative going edge of the clock pulse. All  
inputs are equipped withprotection circuits against static  
discharge and transient excess voltage.  
INPUT AND OUTPUT EQUIVALENT CIRCUIT  
NC =  
No Internal  
Connection  
October 1992  
1/11  

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