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M54HC112_04 PDF预览

M54HC112_04

更新时间: 2024-01-03 21:45:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 257K
描述
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

M54HC112_04 数据手册

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M54HC112  
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR  
HIGH SPEED:  
= 79MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=2µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
DILC-16  
FPC-16  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
FM  
EM  
V
CC  
DILC  
FPC  
M54HC112D  
M54HC112K  
M54HC112D1  
M54HC112K1  
PIN AND FUNCTION COMPATIBLE WITH  
54 SERIES 112  
SPACE GRADE-1: ESA SCC QUALIFIED  
50 krad QUALIFIED, 100 krad AVAILABLE ON  
REQUEST  
NO SEL UNDER HIGH LET HEAVY IONS  
IRRADIATION  
individual J, K, clock, and asynchronous set and  
clear inputs for each flip-flop. When the clock goes  
high, the inputs are enabled and data will be  
accepted. The logic level of the J and K inputs  
may be allowed to change when the clock pulse is  
high and the bistable will function as shown in the  
truth table. Input data is transferred to the input on  
the negative going edge of the clock pulse.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
DEVICE FULLY COMPLIANT WITH  
SCC-9203-051  
DESCRIPTION  
The M54HC112 is an high speed CMOS DUAL  
J-K FLIP-FLOP WITH PRESET AND CLEAR  
2
fabricated with silicon gate C MOS technology.  
The M54HC112 dual JK flip-flop features  
PIN CONNECTION  
March 2004  
1/11  

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