Datasheet > M54HC109_04

M54HC109_04

更新时间： 2024-02-29 18:52:58

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器
页数	文件大小	规格书
10页	180K
描述
RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

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数据手册

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M54HC109_04 数据手册

M54HC109

RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

■

HIGH SPEED :

= 67MHz (TYP.) at V = 6V

MAX

LOW POWER DISSIPATION:

=2µA(MAX.) at T =25°C

HIGH NOISE IMMUNITY:

= V = 28 % V (MIN.)

NIH

NIL

DILC-16

FPC-16

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4mA (MIN)

BALANCED PROPAGATION DELAYS:

ORDER CODES

PACKAGE

PLH

PHL

WIDE OPERATING VOLTAGE RANGE:

(OPR) = 2V to 6V

DILC

FPC

M54HC109D

M54HC109K

M54HC109D1

M54HC109K1

PIN AND FUNCTION COMPATIBLE WITH

54 SERIES 109

■

SPACE GRADE-1: ESA SCC QUALIFIED

50 krad QUALIFIED, 100 krad AVAILABLE ON

REQUEST

NO SEL UNDER HIGH LET HEAVY IONS

IRRADIATION

input this device changes state on positive going

transition of the clock pulse. CLEAR and PRESET

are independent of the clock and are

accomplished by a logic low on the corresponding

input.

All inputs are equipped with protection circuits

against static discharge and transient excess

voltage.

■

DEVICE FULLY COMPLIANT WITH

SCC-9306-048

DESCRIPTION

The M54HC109 is an high speed CMOS DUAL

J-K FLIP FLOP WITH PRESET AND CLEAR

fabricated with silicon gate C MOS technology. In

accordance with the logic level on the J and K

PIN CONNECTION

March 2004

1/10

12 3 4 5 6 7...10

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与M54HC109_04相关器件

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M54HC109D	STMICROELECTRONICS	获取价格	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M54HC109D1	STMICROELECTRONICS	获取价格	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M54HC109F1	STMICROELECTRONICS	获取价格	暂无描述
M54HC109F1R	STMICROELECTRONICS	获取价格	DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M54HC109K	STMICROELECTRONICS	获取价格	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
M54HC109K1	STMICROELECTRONICS	获取价格	RAD-HARD DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
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