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M36LLR8760TT PDF预览

M36LLR8760TT

更新时间: 2024-11-01 22:31:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存静态存储器
页数 文件大小 规格书
19页 429K
描述
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package

M36LLR8760TT 数据手册

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M36LLR8760T1, M36LLR8760D1  
M36LLR8760M1, M36LLR8760B1  
256 + 128 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory  
64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package  
TARGET SPECIFICATION  
FEATURES SUMMARY  
MULTI-CHIP PACKAGE  
Figure 1. Package  
1 die of 256 Mbit (16Mb x16, Multiple  
Bank, Multi-level, Burst) Flash Memory  
1 die of 128 Mbit (8Mb x16, Multiple Bank,  
Multi-Level, Burst) Flash Memory  
FBGA  
1 die of 64 Mbit (4Mb x16) Pseudo SRAM  
SUPPLY VOLTAGE  
V
1.95V  
= V  
= V  
= V  
= 1.7 to  
DDQF  
DDF1  
DDF2  
CCP  
LFBGA88 (ZAQ)  
8 x 10mm  
V
= 9V for fast program (12V tolerant)  
PPF  
ELECTRONIC SIGNATURE  
Manufacturer Code: 20h  
Top Configuration (Top + Top)  
M36LLR8760T1: 880Dh + 88C4h  
Mixed Configuration (Bottom + Top)  
M36LLR8760D1: 880Eh + 88C4h  
Mixed Configuration (Top + Bottom)  
M36LLR8760M1: 880Dh + 88C5h  
COMMON FLASH INTERFACE (CFI)  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
DUAL OPERATIONS  
program/erase in one Bank while read in  
others  
No delay between read and write  
operations  
Bottom Configuration (Bottom + Bottom)  
M36LLR8760B1: 880Eh + 88C5h  
SECURITY  
PACKAGE  
64 bit unique device number  
2112 bit user programmable OTP Cells  
Compliant with Lead-Free Soldering  
Processes  
Lead-Free Versions  
BLOCK LOCKING  
All blocks locked at power-up  
Any combination of blocks can be locked  
with zero latency  
FLASH MEMORIES  
SYNCHRONOUS / ASYNCHRONOUS READ  
WP for Block Lock-Down  
Absolute Write Protection with V  
Synchronous Burst Read mode: 54MHz  
Asynchronous Page Read mode  
Random Access: 85ns  
F
= V  
SS  
PPF  
PSRAM  
SYNCHRONOUS BURST READ SUSPEND  
PROGRAMMING TIME  
ACCESS TIME: 70ns  
ASYNCHRONOUS PAGE READ  
10µs typical Word program time using  
Buffer Enhanced Factory Program  
command  
Page Size: 16 words  
Subsequent read within page: 20ns  
MEMORY ORGANIZATION  
LOW POWER FEATURES  
Multiple Bank Memory Array:  
16 Mbit Banks for the 256 Mbit Memory  
8 Mbit Banks for the 128 Mbit Memory  
Temperature Compensated Refresh  
(TCR)  
Partial Array Refresh (PAR)  
Deep Power-Down (DPD) Mode  
Parameter Blocks (at Top or Bottom)  
SYNCHRONOUS BURST READ/WRITE  
July 2005  
1/19  
This is preliminary information on a new product forseen to be developed. Details are subject to change without notice.  

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