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M36L0R8060B1ZAQF PDF预览

M36L0R8060B1ZAQF

更新时间: 2024-11-18 03:20:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 存储内存集成电路静态存储器
页数 文件大小 规格书
18页 392K
描述
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package

M36L0R8060B1ZAQF 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:BGA包装说明:8 X 10 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-88
针数:88Reach Compliance Code:unknown
HTS代码:8542.32.00.71风险等级:5.06
Is Samacsys:N其他特性:PSEUDO SRAM IS ORGANIZED AS 4M X 16; SYNCHRONOUS BURST MODE OPERATION ALSO POSSIBLE
JESD-30 代码:R-PBGA-B88JESD-609代码:e1
长度:10 mm内存密度:268435456 bit
内存集成电路类型:MEMORY CIRCUIT内存宽度:16
混合内存类型:FLASH+PSRAM功能数量:1
端子数量:88字数:16777216 words
字数代码:16000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-25 °C
组织:16MX16封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA88,8X12,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
峰值回流温度(摄氏度):260电源:1.8 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.00011 A子类别:Other Memory ICs
最大压摆率:0.052 mA最大供电电压 (Vsup):1.95 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:OTHER端子面层:TIN SILVER COPPER
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8 mmBase Number Matches:1

M36L0R8060B1ZAQF 数据手册

 浏览型号M36L0R8060B1ZAQF的Datasheet PDF文件第2页浏览型号M36L0R8060B1ZAQF的Datasheet PDF文件第3页浏览型号M36L0R8060B1ZAQF的Datasheet PDF文件第4页浏览型号M36L0R8060B1ZAQF的Datasheet PDF文件第5页浏览型号M36L0R8060B1ZAQF的Datasheet PDF文件第6页浏览型号M36L0R8060B1ZAQF的Datasheet PDF文件第7页 
M36L0R8060T1  
M36L0R8060B1  
256 Mbit (Multiple Bank, Multi-Level, Burst) Flash Memory  
and 64 Mbit (Burst) PSRAM, 1.8V Supply, Multi-Chip Package  
FEATURES SUMMARY  
MULTI-CHIP PACKAGE  
Figure 1. Package  
1 die of 256 Mbit (16Mb x16, Multiple  
Bank, Multi-level, Burst) Flash Memory  
1 die of 64 Mbit (4Mb x16) Pseudo SRAM  
SUPPLY VOLTAGE  
V
V
= V  
= V  
= 1.7 to 1.95V  
DDF  
PPF  
CCP  
DDQF  
FBGA  
= 9V for fast program (12V tolerant)  
ELECTRONIC SIGNATURE  
Manufacturer Code: 20h  
Top Device Code  
M36L0R8060T1: 880Dh  
TFBGA88 (ZAQ)  
8 x 10mm  
Bottom Device Code  
M36L0R8060B1: 880Eh  
PACKAGE  
Compliant with Lead-Free Soldering  
Processes  
Lead-Free Versions  
FLASH MEMORY  
BLOCK LOCKING  
SYNCHRONOUS / ASYNCHRONOUS READ  
All blocks locked at power-up  
Any combination of blocks can be locked  
with zero latency  
Synchronous Burst Read mode: 54MHz  
Asynchronous Page Read mode  
Random Access: 85ns  
WP for Block Lock-Down  
Absolute Write Protection with V  
F
SYNCHRONOUS BURST READ SUSPEND  
PROGRAMMING TIME  
= V  
SS  
PPF  
COMMON FLASH INTERFACE (CFI)  
100,000 PROGRAM/ERASE CYCLES per  
BLOCK  
10µs typical Word program time using  
Buffer Enhanced Factory Program  
command  
PSRAM  
MEMORY ORGANIZATION  
ACCESS TIME: 70ns  
ASYNCHRONOUS PAGE READ  
Multiple Bank Memory Array: 16 Mbit  
Banks  
Page Size: 16 words  
Subsequent read within page: 20ns  
Parameter Blocks (Top or Bottom  
location)  
DUAL OPERATIONS  
LOW POWER FEATURES  
program/erase in one Bank while read in  
others  
Temperature Compensated Refresh  
(TCR)  
No delay between read and write  
operations  
Partial Array Refresh (PAR)  
Deep Power-Down (DPD) Mode  
SECURITY  
SYNCHRONOUS BURST READ/WRITE  
64 bit unique device number  
2112 bit user programmable OTP Cells  
June 2005  
1/18  

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